Developed a master stack IP core that operates solely in the FPGA logic area.
The "EtherCAT FPGA IP Core Version Master" is software that enables high-speed cyclic communication of less than 100μsec. It mainly includes master functions such as compliance with ETG.1500 class B, cable redundancy features, and DC functions. Please feel free to consult us if you have any requests. 【Features】 ■ Stable communication intervals with jitter around 25nsec ■ CPU area can be freely designed from the OS level ■ Can operate on the customer's design board with the provision of the IP core *For more details, please download the PDF or feel free to contact us.
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【Other EtherCAT Master Lineup】 ■ ARM CPU Version Master ■ ARM CPU & FPGA Version Master *For more details, please download the PDF or feel free to contact us.
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For more details, please download the PDF or feel free to contact us.
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KSJ Corporation has been engaged in contract development and product supply of embedded circuit boards for industrial equipment for over 30 years. For the supplied circuit boards, we conduct various reliability tests in-house to ensure quality. In recent years, we have been particularly focused on development in the EtherCAT field, developing our own EtherCAT master stack, its FPGA implementation, and our own master board, and we are conducting development and transactions with many customers both domestically and internationally.
