A noise figure analyzer capable of characteristic evaluation using LO control and IF control with a dedicated GPIB.
We offer the noise figure analyzer 'N8975A/N4002A', capable of measuring noise figures up to 30dB in the frequency range of 10MHz to 26.5GHz. Using the noise source (N4002A), gain measurements can also be performed. Additionally, simultaneous measurements of noise figure and gain are possible. 【Features】 ■ Noise figure and gain measurements can be executed simultaneously, and data can be displayed, printed, and saved in various formats. ■ It can also be used for the characterization of amplifiers and frequency conversion devices (mixers) using LO control with dedicated GPIB and IF control. *For more details, please download the PDF or feel free to contact us.
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**Main Specifications** ■N8975A Noise Figure Analyzer - Provides a one-box solution with a frequency range of 10MHz-26.5GHz - Equipped with an APC 3.5 (female) connector as standard ■N4002A Noise Source - Frequency range of 10MHz-26.5GHz - Reduction of user errors through electronic storage of ENR calibration data - Overall setup time is shortened by automatically downloading ENR data to the noise figure analyzer - Improved measurement accuracy through temperature compensation, achieving strict performance specifications for devices *For more details, please download the PDF or feel free to contact us.*
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For more details, please download the PDF or feel free to contact us.
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The Fukuoka Prefectural Industrial and Scientific Technology Promotion Foundation's Three-Dimensional Semiconductor Research Center has facilities that can design, manufacture, test, evaluate, and analyze embedded substrates with active and passive components wired in three dimensions within printed circuit boards at mass production levels. In addition to a standard printed circuit board manufacturing line, it is equipped with mounting devices for embedding components within the substrate and high-temperature, high-humidity vibration testing equipment to evaluate connection reliability. Furthermore, there is an 8-inch silicon wafer line that allows for the development of test element group (TEG) chips for evaluation. Additionally, it is possible to develop three-dimensional stacking of chips using through silicon vias (TSV) and silicon interposers that use silicon substrates instead of printed circuit boards.