Reduce CMP grinding burden! Plating is possible for through vias on ceramic substrates and resin substrates.
The "embedded plating technology for vias in wafers" is used for the purpose of improving frequency characteristics, achieving high-density miniaturization, and reducing power consumption, and is also being considered for applications in 5G communications. Our company is capable of metal embedding through plating for both blind vias and through vias. Additionally, we accommodate various via shapes, including straight shapes, constricted shapes, tapered shapes, and wall surface irregularities. 【Features】 ■ Embedding plating without voids is possible ■ Reduces the burden of CMP polishing ■ Compatible with various via shapes ■ Non-destructive confirmation of the embedding state is possible ■ Conformal plating technology *For more details, please refer to the PDF document or feel free to contact us.
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basic information
【Supported Substrates】 ■Size: 4 inch to 8 inch wafers ■Material: Si, SiC, glass, etc. *For more details, please refer to the PDF document or feel free to contact us.
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【Usage】 ■ Interposer (substrate for stacking semiconductor IC chips) ■ 3D mounting substrate *For more details, please refer to the PDF document or feel free to contact us.
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Through the miniaturization of products using our unique nano-plating technology, we promote resource conservation and energy efficiency to protect the global environment, ensuring that even hundreds of billions of components can be produced without a single defect, thereby providing safety and peace of mind to society. This philosophy will be passed down forever as long as the company continues, regardless of how times change. Kiyokawa Plating will continue to provide technology that is always needed by our customers, ensuring their satisfaction and inspiring them.