Achieving a reduction in FPGA development time!
By utilizing the functional verification tool (ModelSim) and conducting simulations from the coding stage, we achieve high quality and reduced development time. *For more details, please refer to the PDF document or feel free to contact us.*
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basic information
Utilize ModelSim for functional verification of FPGA design to quickly analyze discrepancies and bugs in the description. - Verify bugs in the description (Verilog, VHDL) during the coding phase of FPGA design. - Reproduce the same conditions as those inputted in the actual device in the test bench.
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Applications/Examples of results
【ModelSim Utilization Examples】 - Our company creates a simulation test bench simultaneously with the start of development. - Signals input and output to the FPGA are connected to the test bench. - We generate the necessary signals and proceed with work while performing functional verification. - Even with multiple FPGAs, overall simulation is possible. - For example, by connecting FPGA1 output to FPGA2 input, we can confirm the final output through both. - Simulation of irregular cases that cannot be verified in the actual environment is also possible. - Since input signals can be generated freely, verification assuming failure modes of counterpart devices can also be conducted.
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Company information
Our company, as a supporter of social infrastructure, quickly captures market needs and provides products that satisfy our customers. Society as a whole is showing structural changes towards a new normal, accompanied by the acceleration of digital transformation (DX). We are addressing this change by inheriting the technical strengths we have cultivated so far and engaging in research and development to solve social issues and "create a safe and secure society." We focus on advanced technological areas to realize safe, secure, and sustainable social infrastructure.
