We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for core.
ipros is IPROS GMS ・ IPROS One of the largest technical database sites in Japan that collects information on.

core(Core Core) - List of Manufacturers, Suppliers, Companies and Products | IPROS GMS

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

core Product List

31～60 item / All 67 items

Displayed results
[Research Material] Global Market for Ulin Metal Magnetic Cores

[Research Material] Global Market for Ulin Metal Magnetic Cores

World Market for Urine Metal Magnetic Cores: Iron-based, Cobalt-based, Transformers, Inverters, Others

This research report (Global Ulin Metal Magnetic Core Market) investigates and analyzes the current status and outlook for the global market of ulin metal magnetic cores over the next five years. It includes information on the overview of the global ulin metal magnetic core market, trends of major companies (sales, selling prices, market share), market size by segment, market size by major regions, and distribution channel analysis. The segments by type in the ulin metal magnetic core market focus on iron-based and cobalt-based types, while the segments by application target transformers, inverters, and others. The regional segments calculate the market size of ulin metal magnetic cores by dividing them into North America, the United States, Europe, Asia-Pacific, Japan, China, India, South Korea, Southeast Asia, South America, the Middle East, and Africa. It also includes the market share of major companies in the ulin metal magnetic core market, product and business overviews, and sales performance.

  • Other services
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
Aerospace HOLT Corporation 1553 IP Core Demo Kit

Aerospace HOLT Corporation 1553 IP Core Demo Kit

Support for integrating the Holt HI-6300 IP core into Vivado design and FPGA implementation.

In the aerospace industry, reliable data transmission is essential. Particularly in communication under harsh environments, the accuracy and stability of data become crucial. The HI-6300 IP core supports FPGA implementation and provides a solution to enhance the reliability of data transmission. This product demonstrates access to IP bus controller (BC), remote terminal (RT), and monitor (MT) functions using the Holt API library. 【Usage Scenarios】 - Data transmission in aerospace equipment - Development of communication systems using FPGA - Evaluation of the HI-6300 IP core 【Benefits of Implementation】 - Rapid integration into FPGA designs - Improved reliability of data transmission - Reduced development time

  • Development support tools (ICE, emulators, debuggers, etc.)
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T5-17]

High-frequency toroidal core [T5-17]

"Iron powder (ferrous powder) core" 【T5-17】

This is the iron powder core "T5-17" manufactured by MICROMETALS, which is coated for protection.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T12-12]

High-frequency toroidal core [T12-12]

"Iron powder (ferrous powder) core" [T12-12]

This is the "T12-12" iron powder core manufactured by MICROMETALS, which has a protective coating.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
MTP non-volatile memory IP core 'TwinBit'

MTP non-volatile memory IP core 'TwinBit'

No need for complex memory cell configurations! We provide high-performance non-volatile memory at low manufacturing costs.

"TwinBit" is a non-volatile memory IP core that can be manufactured using standard logic processes. It is capable of over 100,000 write cycles across a wide range of processes, from the 0.18um generation to advanced 16nm generation and beyond. It provides high-performance non-volatile memory at a low manufacturing cost without requiring the complex memory cell configurations typical of conventional Flash memory. Customization is also available for various non-volatile memory core applications, ranging from 64-bit latch types to 2MByte code storage memory. 【Features】 ■ World-class smallest memory cell size ■ High-speed, low-power read operation ■ Low-voltage write operation ■ Built-in test circuits *For more details, please refer to the PDF document or feel free to contact us.

  • Memory
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T18-6]

High-frequency toroidal core [T18-6]

"Iron powder (ferrous powder) core"【T18-6】

This is the iron powder core "T14-6" manufactured by MICROMETALS, which has a protective coating.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T20-1]

High-frequency toroidal core [T20-1]

"Iron powder (ferrous powder) core" [T20-1]

This is an iron powder core 【T20-1】 manufactured by MICROMETALS, which has a protective coating.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T14-6]

High-frequency toroidal core [T14-6]

"Iron powder (ferrous powder) core"【T14-6】

This is the iron powder core "T14-6" manufactured by MICROMETALS, which has a protective coating.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T20-2]

High-frequency toroidal core [T20-2]

"Iron powder (ferrous powder) core" [T20-2]

This is an iron powder core 【T20-2】 manufactured by MICROMETALS, which has a protective coating.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T20-6]

High-frequency toroidal core [T20-6]

"Iron powder (ferrous powder) core" [T20-6]

This is an iron powder core 【T20-6】 manufactured by MICROMETALS, coated for protection.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
High-frequency toroidal core [T20-40]

High-frequency toroidal core [T20-40]

"Iron powder (ferrous powder) core" [T20-40]

This is an iron powder core 【T20-40】 manufactured by MICROMETALS, which has a protective coating.

  • Inductor Coil
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
OTP Non-volatile Memory IP Core 'PermSRAM'

OTP Non-volatile Memory IP Core 'PermSRAM'

Achieving affordable and reliable shipping inspections! We support high quality and stable yields.

"PermSRAM" is an OTP non-volatile memory IP core that can be manufactured using standard logic processes. It provides non-volatile memory that can be written only once for a wide range of processes, from the 0.18um generation to advanced 28nm generations and beyond. Customization is possible for various non-volatile memory core applications, ranging from 64b latch types to 1MByte code storage memory. 【Features】 ■ World-class smallest area ■ Reverse engineering resistance ■ Low voltage writing ■ Equipped with test circuits ■ Automotive grade (guaranteed up to 150℃) *For more details, please refer to the PDF document or feel free to contact us.

  • Memory
  • Other electronic parts
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
SATA Device ADCI IP Core for FPGA and ASIC

SATA Device ADCI IP Core for FPGA and ASIC

Supports power modes (partial/slumber)! The DATA interface uses FIFO.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
NVMe-to-NVMe Bridge

NVMe-to-NVMe Bridge

Supports automatic initialization using PCIe hard blocks!

The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
SATA Host AHCI IP Core for FPGA/ASIC

SATA Host AHCI IP Core for FPGA/ASIC

It can widely support systems that require a SATA host!

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore N22"

IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore N15/N15F"

IP core "AndesCore N15/N15F"

It is equipped with an IEEE-754 compliant floating-point unit that enhances floating-point processing capabilities!

The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore D15/D15F"

IP core "AndesCore D15/D15F"

It comes with various configuration options such as MMU, cache, and local memory!

The "AndesCore D15/D15F" is a dual-issue superscalar AndesCore processor. Both processors are equipped with over 130 compiler-friendly general-purpose DSP and SIMD instructions to easily program DSP algorithms in C/C++. They are also designed for a variety of performance-driven applications in embedded Linux, real-time OS, or bare-metal environments. 【Specifications (partial)】 ■ Dual-issue pipeline ■ Over 130 DSP extension instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (D15F) *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore NX25F"

IP core "AndesCore NX25F"

Optimized for high operating frequency and high performance! Supports single-precision/double-precision floating-point instructions.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore N25F"

IP core "AndesCore N25F"

High code density 16/32-bit mixed instruction format!

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore D10"

IP core "AndesCore D10"

The optimized DSP library and C/C++ compiler make programming algorithms easier!

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore N8"

IP core "AndesCore N8"

Reduce memory usage and lower customers' silicon costs!

The "AndesCore N8" is an IP core that provides a long-term roadmap for customers requiring an upgrade path from 8-bit cores. With the ability to process both 16-bit and 32-bit instructions, it enables a reduction in the ROM size of program data. While being a computing platform comparable to an 8-bit controller, it achieves the performance of an advanced 32-bit processor. 【Specifications】 ■ Excellent overall performance ■ Vector interrupts for low-latency interrupt handling ■ Small footprint with fewer gates and high code density ■ Faster Flash access and power reduction through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
5G network slicing and cloud packet core

5G network slicing and cloud packet core

Publication of a 5-year 5G slicing market forecast in seven industries including agriculture, logistics, transportation, healthcare, and finance.

"5G Network Slicing and Cloud Packet Core" is a market research report by ABI Research. This report provides the current and future market size of the 5G slicing market across seven industries: aggregate, logistics, transportation, media & entertainment, utilities, healthcare, and finance. It also includes current market trends in 5G slicing, future changes, revenue distribution of 5G slicing in network connectivity, management and operations, and value-added services. 【Research Highlights (Excerpt)】 ■ Realistic 5-year forecasts for 5G slicing across seven industries ■ Key highlights and investment initiatives necessary for the extensive commercial rollout of 5G slicing ■ 5G slicing market tracker ■ Cloud core network market tracker For more details on the report: https://www.dri.co.jp/auto/report/abi/230731-5g-network-slicing-and.html

  • Other network tools
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore N10"

IP core "AndesCore N10"

You can bridge the internet connection of ZigBee, Bluetooth, or WiFi sensor devices!

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

  • ASIC
  • core

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration

Search Keywords Related to core

COPYRIGHT © 2001-2026 IPROS CORPORATION ALL RIGHTS RESERVED.