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This IP extracts and outputs Frame Start, Frame End, Embedded Data, and Pixel Data from the internal signals of the FPGA after receiving the SLVS-EC signal with the FPGA's Gigabit Transceiver. Additionally, by specifying the maximum number of lanes and the data bus width of the Gigabit Transceiver as parameters, it is possible to optimize resource consumption.
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Free membership registrationWe would like to introduce a development case of the "MIPI Bridge FPGA" using Lattice's CrossLink. CrossLink is a Bridge IC for MIPI interfaces, equipped with two MIPI D-PHY transceivers capable of up to 6Gbps over 4 lanes and 15 pairs of source synchronous I/Os. Our company is engaged in the design of Bridge FPGAs using CrossLink. 【Case Overview】 ■Developed Product: MIPI Bridge FPGA ■Development Details ・MIPI to LVDS conversion ・subLVDS to MIPI conversion ・DSI Splitter *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "High-Speed Real-Time Image Processing Device." Through image processing, we can measure in real-time what the subject is focusing on and display the results. It is capable of measuring at 240fps with two VGA-sized cameras. Additionally, by changing the content of the FPGA image processing, it can be used for various applications. [Case Overview] ■ Developed Product: High-Speed Real-Time Image Processing Device ■ Development Details - Measure in real-time what the subject is focusing on and display the results. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of the "AMD Zynq 7000 All Programmable SoC Image Processing System" that we conducted. Zynq is a device with a new architecture that integrates a Dual Core ARM (Cortex-A9) and a 7-series FPGA. It can connect two cameras. By combining preprocessing with FPGA and post-processing with CPU, we achieve high-speed and high-functionality image processing. 【Case Overview】 ■ Developed Product: AMD Zynq 7000 All Programmable SoC Image Processing System ■ Development Details - By combining preprocessing with FPGA and post-processing with CPU, we achieve high-speed and high-functionality image processing. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "low-latency stereo image synthesis device." Using two cameras synchronized for binocular stereoscopic vision, we output in Side-by-Side format. This allows for real-time display with almost no latency. Additionally, image sensor processing such as demosaicing is executed on the Zynq FPGA. 【Case Overview】 ■ Application: Robot vision, transparent HMD (head-mounted display) ■ Configuration: ZedBoard (AVNET's Zynq board) + D-PHY board (our product) + 2 CMOS sensor modules (e-con Systems) ■ Image Sensor: OmniVision OV5680 (MIPI CSI-2 2lane, 5MPixel 30fps, Full HD 60fps) ■ Output Format: DVI 1280x720 60fps YCbCr422 8bit *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "Dual Image Sensor Equipped Compact Camera Head Board." This board achieves miniaturization with external dimensions of 10mm x 38mm while incorporating two image sensors and two LVDS Tx. The substrate uses FPC. Additionally, since it is equipped with LVDS Tx, it is possible to maintain a distance of over 550mm to the CCU (Camera Control Unit). 【Case Overview】 ■ Developed Product: Dual Image Sensor Equipped Compact Camera Head Board ■ Development Details - Achieved miniaturization with external dimensions of 10mm x 38mm while incorporating two image sensors and two LVDS Tx. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "3D Image Processing Board." This board has the capability to synthesize multiple images and output them to a 3D monitor or external recording device, with input and output compatible with the serial digital interface 3G-SDI used in broadcasting systems. Additionally, 3G-SDI supports both 3D format (3G Level B) and 2D progressive format (3G Level A). [Case Overview] ■ Developed Product: 3D Image Processing Board ■ Development Details - Capable of synthesizing multiple images and outputting them to a 3D monitor or external recording device. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "Wireless Data Collection System for Android Devices." Analog data is converted to digital format on the control device side and transmitted wirelessly to Android devices such as tablets. The same user interface can be used for on-site operations and remote maintenance. Additionally, it is easy to check the operating status of the device, signal waveforms, and set parameters. 【Case Overview】 ■ Developed Product: Wireless Data Collection System for Android Devices ■ Development Details - Analog data is converted to digital format on the control device side and transmitted wirelessly to Android devices such as tablets. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "FPGA Real-Time Super-Resolution Processing System." The system uses an FPGA board for image capture and processing, achieving photon counting-based image measurement and computation in real-time. It performs preprocessing, binarization, labeling, and centroid calculation for camera input of 2048×2048 pixels at 30 fps. Additionally, the processing results undergo a 4×4 super-resolution processing and are output in real-time as an integrated image of 8192×8192 pixels. [Case Overview] ■ Developed Product: FPGA Real-Time Super-Resolution Processing System ■ Development Details: - The system uses an FPGA board for image capture and processing, achieving photon counting-based image measurement and computation in real-time. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "Imaging Device Evaluation System." It consists of a motherboard (ITL-CIEVAS-M) that receives the AD conversion results of data output from a color imaging sensor and outputs it to a PC and an analog display. The ITL-CIEVAS-M comes with standard drawing software (CIEVAS Viewer). Additionally, the drawing software has functions such as defective pixel correction, white balance adjustment, and pixel position correction. 【Case Overview】 ■ Developed Product: Imaging Device Evaluation System ■ Development Details - Composed of a motherboard that receives the AD conversion results of data output from a color imaging sensor and outputs it to a PC and an analog display. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationWe would like to introduce a development case of our "High-Speed CMOS Sensor Evaluation System." Equipped with 4GB of frame memory, it can store approximately 2,000 image data per second. It features an AMD FPGA, specifically the AMD Virtex 5, which handles sensor driving, data reception and storage, as well as sensor image processing (noise reduction). Please feel free to contact us if you have any inquiries. 【Case Overview】 ■ Developed Product: High-Speed CMOS Sensor Evaluation System ■ Development Details - Equipped with 4GB of frame memory, it can store approximately 2,000 image data per second. *For more details, please refer to the related links or feel free to contact us.
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Free membership registrationThis is a board equipped with four MIPI D-PHY ICs (supporting 2.5Gbps) from Meticom. It can receive 2 channels and transmit 2 channels of CSI-2 or DSI signals.
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Free membership registrationWe provide a version of the interface IP for FPGA (SLVS-EC Receiver) Ver2.0, and we can also support FPGA customization and board creation.
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Free membership registrationThe frame grabber "ITL-MU3" quickly captures data from a 2CH image sensor via MIPI CSI-2 and transfers it to a PC at high speed using USB 3.0. The MIPI CSI-2 standard is designed for mobile applications, allowing for power-saving across the entire camera module. 【Features】 ■ Supports MIPI CSI-2: Capable of high-speed capture at 1Gbps per lane, with a maximum of 4Gbps (4 lanes). Includes lane skew adjustment functionality. ■ Can connect MIPI CSI-2 compatible image sensors, camera modules, and camera LSIs in 2 channels. ■ Supports USB 3.0: Data transfer speeds are up to 10 times faster than the conventional USB 2.0 standard, with a maximum of 5Gbps*. ■ Real-time image processing is possible. ■ Customizable. * The maximum transfer speed of 5Gbps is a theoretical value according to the standard. 【Applications】 Evaluation, demonstration, and inspection of image sensors and camera modules. * For more details, please request documentation or view the PDF data available for download.
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Free membership registration● We provide extensive support for your development across all areas of hardware, firmware, and software. ● We have extensive experience in image processing, compression, high-speed transmission, and recognition. ● We achieve high-speed processing and real-time processing through hardware processing using FPGAs.
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Free membership registrationWe can provide interface IP for FPGA (CSI-2 Receiver, CSI-2 Transmitter, DSI Transmitter), as well as customization of FPGA and creation of boards.
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Free membership registrationThis system consists of a driver board (ITL-CIEVAS-D), a motherboard (ITL-CIEVAS-M), and standard drawing software (CIEVAS Viewer).
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