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  3. Image Processing
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  6. [Development Case] Image Processing System

[Development Case] Image Processing System

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last updated:Mar 07, 2024

画像技研
画像技研
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Compact and low power consumption! Equipped with Gigabit Ethernet and USB interface.

We would like to introduce a development case of the "AMD Zynq 7000 All Programmable SoC Image Processing System" that we conducted. Zynq is a device with a new architecture that integrates a Dual Core ARM (Cortex-A9) and a 7-series FPGA. It can connect two cameras. By combining preprocessing with FPGA and post-processing with CPU, we achieve high-speed and high-functionality image processing. 【Case Overview】 ■ Developed Product: AMD Zynq 7000 All Programmable SoC Image Processing System ■ Development Details - By combining preprocessing with FPGA and post-processing with CPU, we achieve high-speed and high-functionality image processing. *For more details, please refer to the related links or feel free to contact us.

    Image Processing Software
スクリーンショット

[Development Case] Image Processing System

スクリーンショット 2024-03-06 165157.png
スクリーンショット 2024-03-06 165157.png
  • Related Link - http://www.gazogiken.co.jp/dev_example.html

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画像技研

画像技研

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● Image Giken assists customers with their development. We provide extensive support for customer development across hardware, FPGA, firmware, and software. If you provide us with a product concept, we can deliver a working prototype. For small lots, mass production supply is also possible. ● Image Giken is an expert in images. Through the development of various cameras and image sensor application devices, we have accumulated know-how in image signal processing. We have also quickly tackled and realized advanced interfaces such as USB 3.0, 3G-SDI (3D format compatible), MIPI (CSI-2 / DSI), and SLVS-EC Ver2.0. By using hardware processing with FPGA, we achieve high-speed processing and real-time processing. We implement real-time noise reduction processing for a 1.3 million pixel 2000fps CMOS image sensor. Additionally, we provide functions such as labeling engines as FPGA IP.

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