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CUnet is a remote I/O control network with a "multi-master: multi-slave" configuration. Up to 64 CUnet ICs can be connected on a single network, and communication between the master and slaves is always automatic. The CUnet ICs are equipped with 512 bytes of memory for both master and slave ICs, and since it is a data-sharing type network, once a communication cycle is completed, the memory information of all CUnet ICs becomes the same (data sharing). Therefore, the CPU connected to the master IC can control the I/O of each slave simply by reading/writing to the memory of the master IC. The network connection uses multi-drop wiring with RS485, but by using a HUB-IC (MKY02), T-branching and wiring extensions are also possible.

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HLS is a remote I/O control network with a "1 master: multiple slaves" configuration. Communication between the master and slaves is automatic, allowing for the connection of up to 63 slave ICs. Multi-drop wiring using RS485 is utilized for connections, but by using a HUB-IC (MKY02), T-branching and wiring extensions are also possible. Additionally, within the master IC, there is a memory area corresponding to each slave IC. This memory area consists of communication control registers for communication status, interrupts, and communication errors, as well as I/O control registers. The CPU can control the I/O connected to each slave IC simply by reading/writing the memory of the master IC.

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【512-byte Shared Memory】 The 512-byte shared memory consists of 64 blocks (1 block is 8 bytes). This 512-byte shared memory is composed of a "self-occupied area" that can only be written to by the CPU connected to the self (CUnet IC) and an area where input data from other CUnet ICs is copied. 【Buffer for Mail Function】 The buffer for the mail function consists of two receive buffers and one send buffer, each of which is 256 bytes. 【Communication Control Register】 This is a register that controls communication such as starting communication, error checking, and sending and receiving mail. By simply accessing this register, it is possible to easily control CUnet communication. Additionally, the MKY43 has two interrupt terminals. It realizes various interrupt functions such as shared memory update interrupts, mail sending interrupts, mail receiving completion interrupts, specific terminal participation interrupts, specific terminal departure interrupts, and communication error occurrence interrupts.

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【DI: Input Operation】 Input data is written to the self-occupied area (1 block = 8 bytes) and is copied to all other CUnet ICs via CUnet communication. 【DO: Output Operation】 Since CUnet is multi-master, it is necessary to set its own master at the DOSA (Data Output Station Address) terminal. Data from the memory area of the master set at DOSA is output. 【I/O Control Without CPU】 DIO control can be realized with a configuration consisting only of MKY46 without a CPU. This is possible because the communication protocol is built into the CUnet ICs. Therefore, development costs can be significantly reduced.

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The MKY36 is a center IC (hereinafter referred to as "master") compatible with HLS (Hi-speed Link System). The MKY36 can be connected to the CPU using an 8-bit or 16-bit bus, allowing access from the CPU. Access to the MKY36 from the CPU can be handled similarly to SRAM, enabling the CPU to control communication and DIO simply by reading/writing to the MKY36's memory. The MKY36 has two receiving terminals (RXD1, RXD2), allowing it to control two RS-485 communication lines. Additionally, it is equipped with two interrupt terminals, enabling various interrupt functions such as input update interrupts and communication error occurrence interrupts. Besides these various interrupt functions, the MKY36 also incorporates a communication protocol, achieving communication functionality that reduces the load on the CPU.

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【DI: Input Operation】 Input data is automatically stored in the I/O control registers (DIN area) corresponding to each slave within the master IC. 【DO: Output Operation】 Output data is automatically output by writing to the I/O control registers (DOUT area) corresponding to each slave within the master IC.

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