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  6. NVMe IP core for FPGA

NVMe IP core for FPGA

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NVMe-IP

last updated:Oct 13, 2020

デザイン・ゲートウェイ
デザイン・ゲートウェイ
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Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.

The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Time-limited bit/sof files for various Xilinx/Intel FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase.

    ASIC
KCU105_NVMe.jpg

NVMe IP core for FPGA

KCU105_NVMe.jpg
KCU105_NVMe.jpg
  • Related Link - http://www.dgway.com/NVMe-IP_X.html

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basic information

- Implementation of an application layer to access NVMe PCI Express SSDs - Simple user control interface and FIFO interface for data ports - Built-in 256K byte data buffer in the core constructed with BRAM - Supports six commands - IDENTIFY, WRITE, READ, Shutdown, SMART, Flush - Preparation of evaluation adapter boards AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR - Provision of NVMeG4-IP (built-in version of PCIe Gen4 Soft IP), compatible with devices without PCIe Hard IP (Gen3 version also available) - raNVMe-IP achieves over 500K IOPS random access without a CPU - Compatible with PCIe switches (customized individual support available; please inquire for details) - Access to exFAT/FAT32 file systems without a CPU (optional) - Reference project that operates on actual hardware included with the product, with all source code provided except for the core - Reliable domestic support

Price range

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Delivery Time

P3

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Applications/Examples of results

The NVMe-IP core enables connection with various form factor SSDs. For example, by integrating NVMe-IP and data acquisition user logic into an FPGA, data can be recorded onto an M.2 SSD, achieving an ultra-compact and ultra-fast data acquisition system. raNVMe-IP achieves over 500K IOPS of random (write) access to high-performance NVMe SSDs without using a CPU. raNVMe-IP is ideal for applications that require multiple simultaneous accesses to NVMe SSDs at peak performance, such as high-speed SSD database search systems.

Detailed information

  • NVMe-blockV3.png

    NVMe-IP Block Diagram No CPU or external memory required, optimized PCIe bridge integrated

Line up(6)

Model number overview
NVMe-IP-ZUP NVMe-IP core compatible with Zynq UltraScale+
NVMe-IP-VUP NVMe-IP core compatible with Virtex UltraScale+
NVMe-IP-KU NVMe-IP compatible with Kintex UltraScale
NVMe-IP-VT7 NVMe-IP compatible with Virtex-7
NVMe-IP-A10SX NVMe-IP compatible with Arria10SX
NVMe-IP-A10GX NVMe-IP compatible with Arria10GX

catalog(3)

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NVMe-IP Core Leaflet

NVMe-IP Core Leaflet

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Design Gateway Comprehensive Catalog (Xilinx Edition)

Design Gateway Comprehensive Catalog (Xilinx Edition)

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Design Gateway Comprehensive Catalog (Intel Version)

Design Gateway Comprehensive Catalog (Intel Version)

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Company information

デザイン・ゲートウェイ

デザイン・ゲートウェイ

Electronic Components and Semiconductors

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Design Gateway is a pioneer in the development and sales of advanced IP cores, with over 30 years of experience in the FPGA industry.

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