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  6. TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

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TOE100G-IP

last updated:Mar 22, 2021

デザイン・ゲートウェイ
デザイン・ゲートウェイ
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Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

    ASIC
TOE100G-IPblock.jpg

TOE100G-IP core for FPGA

TOE100G-IPblock.jpg
TOE100G-IPblock.jpg
  • Related Link - http://www.dgway.com/TOE100G-IP_X.html

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basic information

■Supports simultaneous transmission and reception of TCP 100GbE (Full Duplex) ■Pure hardware-wired TCP/IP protocol stack ■Single session connection ■Supports both server and client modes (passive/active open/close) ■High-speed processing for transmission and reception ■Supports jumbo frames (during transmission) ■Transmission/reception buffer size can be adjusted to optimal points based on resource consumption and performance ■User-friendly interface (data I/F is FIFO type, control I/F is register type) ■Supports IPv4 ■Evaluation boards from Xilinx/Intel can be used for core evaluation before purchase ■Includes a reference project that operates on the actual device, with all source code provided except for the core ■Reliable domestic support

Price range

P6

Delivery Time

P3

※It is necessary to conclude a license agreement.

Applications/Examples of results

The TOE100G-IP core is an optimal solution for applications that require high-speed transfer of large amounts of data, such as video and storage. (Application examples) ■ Multi-channel HD video streaming ■ Autonomous driving development systems composed of multi-channel cameras, LIDAR, radar, and sensors ■ Medical scanners such as MRI and PET scans

Detailed information

  • TOE100G-IPblock.jpg

    TOE100G-IP Block Diagram

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Model number overview
TOE100G-IP-ALV TOE100G-IP compatible with ALVEO
TOE100G-IP-KUP TOE100G-IP compatible with Kintex Ultrascale+

catalog(3)

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Design Gateway Comprehensive Catalog (Intel Version)

Design Gateway Comprehensive Catalog (Intel Version)

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Design Gateway Comprehensive Catalog (Xilinx Edition)

Design Gateway Comprehensive Catalog (Xilinx Edition)

CATALOG
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CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog

CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog

PRODUCT
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Company information

デザイン・ゲートウェイ

デザイン・ゲートウェイ

Electronic Components and Semiconductors

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Design Gateway is a pioneer in the development and sales of advanced IP cores, with over 30 years of experience in the FPGA industry.

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