Demo kit ADK-6300 to support FPGA implementation by integrating Holt's HI-6300 IP core into Vivado design.
This kit is provided to integrate the HI-6300 IP core into Vivado designs and assist with FPGA implementation. The accompanying software demonstrates access to the IP's bus controller (BC), remote terminal (RT), and monitor (MT) functions using the Holt API library. This demonstration uses the Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit. The embedded ARM Cortex-A53 interfaces with the HI-6300 IP core via the AXI4 bus and runs the demonstration software. The demo project is a bare-metal implementation using the Holt API software library. This software can be accessed from a terminal console via the USB/UART connector.
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basic information
Contents of the evaluation kit: - Application note - Holt HI-6300 software project and documentation saved on USB flash drive - HI-6300 API demo sample project (including API runtime library) - Daughter card for ADK-6300 IP core kit (EV-1587DC) PC requirements: Linux or Windows OS: Ubuntu 18.04.3 LTS or later / Windows 7 or later System RAM: 16GB for Vivado Hard drive capacity: 10GB or more for Vivado/Vitis projects USB 2.0 or 3.0 port: for FPGA programming and USART communication
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MIL-STD-1553 terminal equipment, flight control and monitoring, sensor interface, test equipment
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"Naser" is a term quoted from "If you try, you can achieve; if you don't try, you won't achieve, in anything." It represents the spirit of challenging oneself to pursue what one believes in, even if success is not guaranteed. Our policy at Naser is "WIN-WIN-WIN." This means that our goal is for all parties involved—customers, product suppliers, and Naser—to achieve "good results from our work." Naser challenges this goal as an electronics import trading company.
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