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  6. Enlarge/Reduce IP Core (Verilog)

Enlarge/Reduce IP Core (Verilog)

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P1_Scale

last updated:Sep 02, 2009

メティエ
メティエ
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Enlarge/Reduce IP Core (Verilog)

P1_Scale performs image scaling using multi-rate signal processing in hardware. The maximum image size is 1024x1024, and the scaling ratio is N/M where N and M can be 1, 2, 3, 4, 5, 6, 7, or 8.

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Enlarge/Reduce IP Core (Verilog)

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P1_Scale performs image scaling using multi-rate signal processing in hardware. The maximum image size is 1024x1024. The scaling ratio N/M where N, M = 1, 2, 3, 4, 5, 6, 7, 8.

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Applying multi-rate signal processing technology to image processing allows for resizing with higher image quality than interpolation methods like bilinear. Thumbnail creation for photos with a large reduction ratio can also be accelerated through hardware processing.

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Enlarge/Reduce IP Core (Verilog)

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ASIC and FPGA Design We conduct consistent development from evaluation using FPGA to the design of dedicated ICs. We have extensive experience, particularly in the fields of imaging and image processing systems for LCD displays. Embedded Software Development We develop embedded programs that efficiently utilize hardware resources. We specialize in development using CPUs embedded in FPGAs. Printed Circuit Board Design We design patterns for stable operation and power supply circuits for high-speed, multi-pin FPGA circuit boards. Additionally, we are capable of designing printed circuit boards for LED lighting devices, which is a technology gaining attention in recent years.

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