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Core(Core Core) - メーカー・企業と製品の一覧

更新日： 集計期間:Nov 19, 2025～Dec 16, 2025
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Coreの製品一覧

16～30 件を表示 ／ 全 65 件

表示件数
IEEE1588-2008 PTP Time Synchronization IP Core

IEEE1588-2008 PTP Time Synchronization IP Core

Providing IEEE1588-2008 PTP time synchronization solutions as an IP core. Synchronizing devices on Ethernet (LAN) with nanosecond precision.

Oregano Systems offers timing synchronization solutions compliant with IEEE1588-2008 Precision Time Protocol as IP CORE. It provides syn1588 Clock_S for serial connection to external CPUs and syn1588 Clock_M for parallel connection, available in netlist or source code. Synchronization in the nanosecond range over Ethernet is possible. Support for 802.1AS will be available starting summer 2016.

  • syn1588 Clock_M GMII.jpg
  • LAN construction and wiring work

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ZIA ISP Optimal Small IP for AI Camera System

ZIA ISP Optimal Small IP for AI Camera System

This is an IP product that realizes high image quality and high performance for AI camera systems.

Compatible with Sony's IMX390 image sensor HDR functionality, it can support high-sensitivity cameras with low noise and a wide dynamic range even in harsh environments such as rain, fog, and backlighting. It can be utilized in products that require high visibility, such as mobility, safety support systems, and surveillance systems. Product introduction manufacturer website: https://www.dmprof.com/ja/products-and-services/ai-products/hardware/ip-core/zia-isp.html

  • Other semiconductors

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DapTechnology's FireGate PHY Layer Core

DapTechnology's FireGate PHY Layer Core

FireGate is an IP core that complies with IEEE-1394b and supports all AS5643 requirements.

Advantages of implementing a complete 1394 I/O interface using FPGA Standalone solution: By combining PHY IP with link layer IP, it is possible to create smaller products. Additional components can be added to create a system-on-chip (SoC) solution. Flexible number of ports: Commercially available PHY chips have a fixed number of ports, which is often excessive for small peripherals. On the other hand, host adapters are likely to benefit from three or more ports, and hubs can have even more ports. In the case of PHY based on FPGA technology, users can customize the number of ports as needed. Optional debugging and testing features: Optionally, debugging and testing features such as BERT (Bit Error Rate Testing) can be included. Field upgradable: The FPGA used is field-upgradable, allowing new features and bug fixes to be added even when the device is already in the field. Cost-effective ASICs: Once the design is complete, the IP solution provides a very cost-effective way to spin custom ASICs.

  • others

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DapTechnology FireCore (IP Core)

DapTechnology FireCore (IP Core)

FireCore is an IP core that integrates PHY and link layer controller (LLC) cores into a single IP product.

FireCore integrates the PHY and link layer requirements necessary for common 1394 devices into a single IP core. Based on the FireGate PHY IP core and FireLink LLC IP core, FireCore is designed to support data rates from S100 to S3200 and various host interfaces such as generic, OHCI, and OHCI (with AS5643 option). DapTechnology's new FireCore package offers unprecedented technical capabilities, features, flexibility, and options for customization and future expansion. Together with FireStack (DapTechnology's 1394 software stack), FireCore is designed to fully leverage the capabilities of the AS5643 extension. It aims to completely abstract the 1394 protocol layer and the AS5643 protocol layer, allowing implementers to focus entirely on system-level functionalities such as fault tolerance, fault isolation, and redundancy.

  • others

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IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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Dynamic Neural Accelerator(DNA)

Dynamic Neural Accelerator(DNA)

Seamlessly accelerate increasingly complex compute-intensive AI workloads!

The "Dynamic Neural Accelerator (DNA)" is a flexible deep learning inference IP core characterized by high computational power, ultra-low latency, and a scalable inference engine. While boasting excellent power efficiency compared to other standard processors, it achieves ultra-low latency for inference in streaming data. Please feel free to contact us if you have any inquiries. 【Features】 ■ Ultra-low latency AI inference IP core ■ Robust open-source MERA software framework ■ Compatible with both FPGA and ASIC/SoC (The photo and link below show an example of DNA mounted on the Bittware (Molex Japan) FPGA card IA420F.) *For more details, please refer to the link below, download the PDF, or contact us. Reference link: https://www.bittware.com/ja/ip-solutions/edgecortix-dynamic-neural-accelerator/

  • others

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Winding core ABS core - ABS CORE -

Winding core ABS core - ABS CORE -

Precision molding designed for use in clean rooms.

ABS core excels in cleanliness and molding precision, making it a product that meets the needs of manufacturing environments where high precision is required, such as in clean rooms for electronic materials and packaging films for food and pharmaceuticals.

  • Bag making machine/slitter
  • Vacuum Packaging Machine
  • Injection Molding Machine

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Winding core PE core - PE CORE -

Winding core PE core - PE CORE -

Achieves moderate strength and ease of cutting with a paper tube cutter.

PE core excels in cleanliness and molding precision, making it a product that meets the needs of manufacturing environments where high precision is required, such as in clean rooms for electronic materials and packaging films for food and pharmaceuticals.

  • Bag making machine/slitter
  • Sealing machine
  • Other packaging machines

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[Siliconarts] Raytracing GPU IP

[Siliconarts] Raytracing GPU IP

The world's first real-time Ray tracing & Path tracing GPU IP.

A fabless company that owns raytracing GPU IP and is planning to develop artificial intelligence models and AI processors for edge devices as a new business. For chip development, basic logic design is conducted internally, while backend design is primarily carried out through foundry design houses. [RayCore MC] - MIMD-based low-power high-performance real-time raytracing & path tracking GPU - Achieves real-time low-power raytracing functionality.

  • Other semiconductors

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AES-CTR Encryption IP Core

AES-CTR Encryption IP Core

Compatible with OpenSSL's AES-256-CTR encryption mode! Multiple independent data streams.

The "AES-CTR Encryption IP Core" is an IP core for AES-CTR (Counter Mode) encryption that allows users to perform encryption/decryption of packets or data streams. It supports AES-CTR encryption levels of 128 or 256 bits and enables data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. Additionally, it is compatible with OpenSSL's AES-256-CTR encryption mode. 【Specifications】 ■ AES encryption key can be selected from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput ■ Compatible with OpenSSL's AES-256-CTR encryption mode *For more details, please download the PDF or feel free to contact us.

  • ASIC

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HDMI Receiver Link IP Core "SLISIHDMI"

HDMI Receiver Link IP Core "SLISIHDMI"

It can be easily integrated into SoCs such as HD TVs and AV receivers.

The HDMI receiver link IP core "SLISIHDMI" complies with the HDMI 1.3a standard, and when connected to the HDMI Receiver PHY IP SLIPHDMIR, it can most efficiently leverage the performance of the SLISIHDMIR HDMI Rx IP. Additionally, it is possible to customize the functions of the SLISIHDMIR HDMI Rx IP according to your requirements. For more details, please contact us.

  • Microcomputer

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SAS Initiator IP Core for FPGA/ASIC

SAS Initiator IP Core for FPGA/ASIC

OOB sequence and speed negotiation sequence support!

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC

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Error Correction Code "Reed-Solomon Encoder/Decoder"

Error Correction Code "Reed-Solomon Encoder/Decoder"

Error correction code with the option to add bit/byte interleaving function.

The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding using the Reed-Solomon method, which is used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, primitive polynomial, and generator polynomial can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.

  • Other network tools
  • others

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FPGA-compatible MECHATROLINK communication IP 'SYM3A'

FPGA-compatible MECHATROLINK communication IP 'SYM3A'

Mechatrolink communication macros can be implemented on intel-FPGA.

This is a soft IP that enables the implementation of the MECHATOROLINK-III communication protocol on FPGA. It flexibly accommodates the addition of various interfaces and peripheral circuits, which are features of FPGAs, and allows for easy design integration using the GUI of the Qsys system integration tool. The basic functionality of this IP is equivalent to Yaskawa Electric's JL-100/JL-102. It is easy to build an evaluation environment by combining the Macnica Sodia board with our SY-M3-03 board. High functionality and high-speed processing are achieved through cooperative operation between the ARM Cortex-A9 and user circuits (ARM is used when employing Intel FPGA SoC). * Operation has been confirmed on the Macnica Sodia-Cyclone V ST SoC evaluation board. ■ Supports C1 master/slave/multi-slave configurations ■ Netlist provided as a Soft-IP core ■ MECHATROLINK-III certification obtained

  • Other semiconductors

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[Research Material] Global Market for Amorphous Alloy Cores

[Research Material] Global Market for Amorphous Alloy Cores

Global Market for Amorphous Alloy Cores: High Voltage Transformer Cores, Low Voltage Transformer Cores, Electronics, New Energy, Aerospace, Aviation, Communication

This research report (Global Amorphous Alloy Core Market) investigates and analyzes the current status and outlook for the global market of amorphous alloy cores over the next five years. It includes information on the overview of the global amorphous alloy core market, trends of major companies (sales, selling prices, market share), market size by segment, market size by major regions, and distribution channel analysis. The market segments by type include high-power distribution transformer cores and low-power distribution transformer cores, while the segments by application cover electronics, new energy, aerospace, aviation, and telecommunications. The regional segments are divided into North America, the United States, Europe, Asia-Pacific, Japan, China, India, South Korea, Southeast Asia, South America, the Middle East, and Africa to calculate the market size of amorphous alloy cores. It also includes the market share of major companies in the amorphous alloy core sector, product and business overviews, and sales performance.

  • Other services

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