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Core(Core Core) - List of Manufacturers, Suppliers, Companies and Products

Last Updated： Aggregation Period:Nov 19, 2025～Dec 16, 2025
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Core Product List

46～60 item / All 65 items

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IP core "AndesCore N15/N15F"

IP core "AndesCore N15/N15F"

It is equipped with an IEEE-754 compliant floating-point unit that enhances floating-point processing capabilities!

The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D15/D15F"

IP core "AndesCore D15/D15F"

It comes with various configuration options such as MMU, cache, and local memory!

The "AndesCore D15/D15F" is a dual-issue superscalar AndesCore processor. Both processors are equipped with over 130 compiler-friendly general-purpose DSP and SIMD instructions to easily program DSP algorithms in C/C++. They are also designed for a variety of performance-driven applications in embedded Linux, real-time OS, or bare-metal environments. 【Specifications (partial)】 ■ Dual-issue pipeline ■ Over 130 DSP extension instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (D15F) *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore NX25F"

IP core "AndesCore NX25F"

Optimized for high operating frequency and high performance! Supports single-precision/double-precision floating-point instructions.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N25F"

IP core "AndesCore N25F"

High code density 16/32-bit mixed instruction format!

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D10"

IP core "AndesCore D10"

The optimized DSP library and C/C++ compiler make programming algorithms easier!

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N8"

IP core "AndesCore N8"

Reduce memory usage and lower customers' silicon costs!

The "AndesCore N8" is an IP core that provides a long-term roadmap for customers requiring an upgrade path from 8-bit cores. With the ability to process both 16-bit and 32-bit instructions, it enables a reduction in the ROM size of program data. While being a computing platform comparable to an 8-bit controller, it achieves the performance of an advanced 32-bit processor. 【Specifications】 ■ Excellent overall performance ■ Vector interrupts for low-latency interrupt handling ■ Small footprint with fewer gates and high code density ■ Faster Flash access and power reduction through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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5G network slicing and cloud packet core

5G network slicing and cloud packet core

Publication of a 5-year 5G slicing market forecast in seven industries including agriculture, logistics, transportation, healthcare, and finance.

"5G Network Slicing and Cloud Packet Core" is a market research report by ABI Research. This report provides the current and future market size of the 5G slicing market across seven industries: aggregate, logistics, transportation, media & entertainment, utilities, healthcare, and finance. It also includes current market trends in 5G slicing, future changes, revenue distribution of 5G slicing in network connectivity, management and operations, and value-added services. 【Research Highlights (Excerpt)】 ■ Realistic 5-year forecasts for 5G slicing across seven industries ■ Key highlights and investment initiatives necessary for the extensive commercial rollout of 5G slicing ■ 5G slicing market tracker ■ Cloud core network market tracker For more details on the report: https://www.dri.co.jp/auto/report/abi/230731-5g-network-slicing-and.html

  • Other network tools

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IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N10"

IP core "AndesCore N10"

You can bridge the internet connection of ZigBee, Bluetooth, or WiFi sensor devices!

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore A25MP"

IP core "AndesCore A25MP"

Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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