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core Product List

31～35 item / All 35 items

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IP core for FPGA/ASIC NVMe Target

IP core for FPGA/ASIC NVMe Target

Register access from the processor is available! Command interrupt support is included.

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe-to-SATA Bridge

NVMe-to-SATA Bridge

Available for LBA remapping, data encryption, data compression, and endpoint aggregation!

We would like to introduce the 'NVMe-to-SATA Bridge' handled by Fujisoft Inc. This product is an IP core for creating an NVMe-to-SATA protocol bridge using NVMe Host IP core and SATA AHCI Host IP core. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. 【Specifications (Excerpt)】 ■ NVMe protocol interface complies with NVMe 1.4 standard ■ SATA interface complies with SATA 3.3 specification ■ Supports industry-standard AHCI (Advanced Host Controller Interface) v.1.3.1 ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks *For more details, please download the PDF or feel free to contact us.

  • ASIC

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ECC with BCH Algorithm IP Core

ECC with BCH Algorithm IP Core

Configurable encoding/decoding block! Parallelized BCH encoder/decoder.

The "ECC with BCH Algorithm IP Core" is an IP core designed to add error detection/correction functionality using industry-standard BCH class error correction codes, preventing data loss or corruption over noisy and unreliable communication channels. If the BCH configuration is not covered, it can be customized to support a wide range of BCH codes. It can be used in a variety of applications, including data storage devices (SATA, SAS, FLASH), two-dimensional barcodes, satellite communication/telemetry, radio signal recording, wireless communication, high-speed modems such as ADSL and xDSL, and power line standards. 【Specifications】 ■ High bandwidth and low latency through parallel processing ■ Configurable encoding/decoding block structure ■ Configurable word length/block size ■ FIFO data interface of 32, 64, 128, or 256 ■ Parallelized BCH encoder/decoder *For more details, please download the PDF or feel free to contact us.

  • ASIC

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AES-XTS Encryption IP Core

AES-XTS Encryption IP Core

You can choose the AES encryption key from 128 or 256 bits! The encryption algorithm complies with FIPS-197.

We would like to introduce the 'AES-XTS Encryption IP Core' that we handle. This product is an AES-XTS encryption IP core that enables full disk encryption for storage devices. It supports AES-XTS encryption levels of 128-bit or 256-bit and allows encryption tailored to data transfer rates of SATA 6Gbps, SAS 12Gbps, and PCIe (NVMe) Gen4 x4 lanes. 【Specifications】 ■ FIPS-197 compliant AES-XTS algorithm ■ AES encryption key selectable from 128 or 256 bits ■ Configurable number of encoding/decoding pipelines ■ Independent management of encryption/decryption keys ■ Simultaneous support for encoding and decoding ■ Supports integer multiples of 16-byte data unit sizes *For more details, please download the PDF or feel free to contact us.

  • ASIC

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AES-CTR Encryption IP Core

AES-CTR Encryption IP Core

Compatible with OpenSSL's AES-256-CTR encryption mode! Multiple independent data streams.

The "AES-CTR Encryption IP Core" is an IP core for AES-CTR (Counter Mode) encryption that allows users to perform encryption/decryption of packets or data streams. It supports AES-CTR encryption levels of 128 or 256 bits and enables data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. Additionally, it is compatible with OpenSSL's AES-256-CTR encryption mode. 【Specifications】 ■ AES encryption key can be selected from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput ■ Compatible with OpenSSL's AES-256-CTR encryption mode *For more details, please download the PDF or feel free to contact us.

  • ASIC

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