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core Product List

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NVMe Host Accelerator IP Core

It is an application layer equipped with an interface to the processor!

We would like to introduce the "NVMe Host Accelerator IP Core" that we handle. This product is an NVMe host IP core from IntelliProp that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) with 8 lanes. It also features queuing and issuing capabilities for NVMe commands, allowing you to use it as a solution for high-speed data access to NVMe target devices. 【Specifications (excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Supports automatic initialization using PCIe hard blocks ■ Compatible with third-party PCIe Root Complex IP cores ■ Number of queues is adjustable (up to 64K) ■ Maximum data buffer size of 1GB *For more details, please download the PDF or feel free to contact us.

  • ASIC

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IntelliProp's IP cores for FPGA and ASIC.

Providing high-quality and high-performance IP core products for the storage industry! Supporting the development of ASSP products as well.

IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*

  • Embedded Board Computers
  • Other network tools
  • Other embedded systems (software and hardware)

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Nanocrystal Core

It is extremely effective for countermeasures against conducted noise below 150 kHz! A large size has also been added to the lineup, making it compatible with large-diameter cables.

Product Outline and Features It has excellent impedance characteristics below 150kHz. High permeability contributes to the miniaturization of the core. It ensures stable impedance characteristics over a wide temperature range. A larger size has been added to the lineup, making it compatible with large diameter cables.

  • Magnetic field analysis/electromagnetic wave analysis
  • EMC Testing
  • Anti-static products

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SATA Device ADCI IP Core for FPGA and ASIC

Supports power modes (partial/slumber)! The DATA interface uses FIFO.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SATA Host AHCI IP Core for FPGA/ASIC

It can widely support systems that require a SATA host!

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC

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DapTechnology FireCore (IP Core)

FireCore is an IP core that integrates PHY and link layer controller (LLC) cores into a single IP product.

FireCore integrates the PHY and link layer requirements necessary for common 1394 devices into a single IP core. Based on the FireGate PHY IP core and FireLink LLC IP core, FireCore is designed to support data rates from S100 to S3200 and various host interfaces such as generic, OHCI, and OHCI (with AS5643 option). DapTechnology's new FireCore package offers unprecedented technical capabilities, features, flexibility, and options for customization and future expansion. Together with FireStack (DapTechnology's 1394 software stack), FireCore is designed to fully leverage the capabilities of the AS5643 extension. It aims to completely abstract the 1394 protocol layer and the AS5643 protocol layer, allowing implementers to focus entirely on system-level functionalities such as fault tolerance, fault isolation, and redundancy.

  • others

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DapTechnology's FireGate PHY Layer Core

FireGate is an IP core that complies with IEEE-1394b and supports all AS5643 requirements.

Advantages of implementing a complete 1394 I/O interface using FPGA Standalone solution: By combining PHY IP with link layer IP, it is possible to create smaller products. Additional components can be added to create a system-on-chip (SoC) solution. Flexible number of ports: Commercially available PHY chips have a fixed number of ports, which is often excessive for small peripherals. On the other hand, host adapters are likely to benefit from three or more ports, and hubs can have even more ports. In the case of PHY based on FPGA technology, users can customize the number of ports as needed. Optional debugging and testing features: Optionally, debugging and testing features such as BERT (Bit Error Rate Testing) can be included. Field upgradable: The FPGA used is field-upgradable, allowing new features and bug fixes to be added even when the device is already in the field. Cost-effective ASICs: Once the design is complete, the IP solution provides a very cost-effective way to spin custom ASICs.

  • others

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DapTechnology FireLink LLC IP Core

FireLink is a link layer controller IP core compliant with IEEE-1394b.

FireLink, a synthesizable IEEE-1394-2008 beta link layer controller (LLC) core, is based on the link layer controller that has been used in DapTechnology's FireSpy analyzer products for several years. FireLink is a mature core implemented on FPGAs from Xilinx, Altera, and Microsemi. FireLink is available in three configurations: Basic, Extended, and GPLink. ■Japanese technical documentation for AS5643 is available. If you would like to see it, please contact sales@nacelle.co.jp■

  • others

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IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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