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IP Cores(Core Core) - List of Manufacturers, Suppliers, Companies and Products

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
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IP Cores Product List

16～30 item / All 46 items

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[Siliconarts] Raytracing GPU IP

[Siliconarts] Raytracing GPU IP

The world's first real-time Ray tracing & Path tracing GPU IP.

A fabless company that owns raytracing GPU IP and is planning to develop artificial intelligence models and AI processors for edge devices as a new business. For chip development, basic logic design is conducted internally, while backend design is primarily carried out through foundry design houses. [RayCore MC] - MIMD-based low-power high-performance real-time raytracing & path tracking GPU - Achieves real-time low-power raytracing functionality.

  • Other semiconductors

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AES-CTR Encryption IP Core

AES-CTR Encryption IP Core

Compatible with OpenSSL's AES-256-CTR encryption mode! Multiple independent data streams.

The "AES-CTR Encryption IP Core" is an IP core for AES-CTR (Counter Mode) encryption that allows users to perform encryption/decryption of packets or data streams. It supports AES-CTR encryption levels of 128 or 256 bits and enables data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. Additionally, it is compatible with OpenSSL's AES-256-CTR encryption mode. 【Specifications】 ■ AES encryption key can be selected from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput ■ Compatible with OpenSSL's AES-256-CTR encryption mode *For more details, please download the PDF or feel free to contact us.

  • ASIC

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HDMI Receiver Link IP Core "SLISIHDMI"

HDMI Receiver Link IP Core "SLISIHDMI"

It can be easily integrated into SoCs such as HD TVs and AV receivers.

The HDMI receiver link IP core "SLISIHDMI" complies with the HDMI 1.3a standard, and when connected to the HDMI Receiver PHY IP SLIPHDMIR, it can most efficiently leverage the performance of the SLISIHDMIR HDMI Rx IP. Additionally, it is possible to customize the functions of the SLISIHDMIR HDMI Rx IP according to your requirements. For more details, please contact us.

  • Microcomputer

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SAS Initiator IP Core for FPGA/ASIC

SAS Initiator IP Core for FPGA/ASIC

OOB sequence and speed negotiation sequence support!

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC

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Error Correction Code "Reed-Solomon Encoder/Decoder"

Error Correction Code "Reed-Solomon Encoder/Decoder"

Error correction code with the option to add bit/byte interleaving function.

The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding using the Reed-Solomon method, which is used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, primitive polynomial, and generator polynomial can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.

  • Other network tools
  • others

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FPGA-compatible MECHATROLINK communication IP 'SYM3A'

FPGA-compatible MECHATROLINK communication IP 'SYM3A'

Mechatrolink communication macros can be implemented on intel-FPGA.

This is a soft IP that enables the implementation of the MECHATOROLINK-III communication protocol on FPGA. It flexibly accommodates the addition of various interfaces and peripheral circuits, which are features of FPGAs, and allows for easy design integration using the GUI of the Qsys system integration tool. The basic functionality of this IP is equivalent to Yaskawa Electric's JL-100/JL-102. It is easy to build an evaluation environment by combining the Macnica Sodia board with our SY-M3-03 board. High functionality and high-speed processing are achieved through cooperative operation between the ARM Cortex-A9 and user circuits (ARM is used when employing Intel FPGA SoC). * Operation has been confirmed on the Macnica Sodia-Cyclone V ST SoC evaluation board. ■ Supports C1 master/slave/multi-slave configurations ■ Netlist provided as a Soft-IP core ■ MECHATROLINK-III certification obtained

  • Other semiconductors

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MTP non-volatile memory IP core 'TwinBit'

MTP non-volatile memory IP core 'TwinBit'

No need for complex memory cell configurations! We provide high-performance non-volatile memory at low manufacturing costs.

"TwinBit" is a non-volatile memory IP core that can be manufactured using standard logic processes. It is capable of over 100,000 write cycles across a wide range of processes, from the 0.18um generation to advanced 16nm generation and beyond. It provides high-performance non-volatile memory at a low manufacturing cost without requiring the complex memory cell configurations typical of conventional Flash memory. Customization is also available for various non-volatile memory core applications, ranging from 64-bit latch types to 2MByte code storage memory. 【Features】 ■ World-class smallest memory cell size ■ High-speed, low-power read operation ■ Low-voltage write operation ■ Built-in test circuits *For more details, please refer to the PDF document or feel free to contact us.

  • Memory

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OTP Non-volatile Memory IP Core 'PermSRAM'

OTP Non-volatile Memory IP Core 'PermSRAM'

Achieving affordable and reliable shipping inspections! We support high quality and stable yields.

"PermSRAM" is an OTP non-volatile memory IP core that can be manufactured using standard logic processes. It provides non-volatile memory that can be written only once for a wide range of processes, from the 0.18um generation to advanced 28nm generations and beyond. Customization is possible for various non-volatile memory core applications, ranging from 64b latch types to 1MByte code storage memory. 【Features】 ■ World-class smallest area ■ Reverse engineering resistance ■ Low voltage writing ■ Equipped with test circuits ■ Automotive grade (guaranteed up to 150℃) *For more details, please refer to the PDF document or feel free to contact us.

  • Memory
  • Other electronic parts

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SATA Device ADCI IP Core for FPGA and ASIC

SATA Device ADCI IP Core for FPGA and ASIC

Supports power modes (partial/slumber)! The DATA interface uses FIFO.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe-to-NVMe Bridge

NVMe-to-NVMe Bridge

Supports automatic initialization using PCIe hard blocks!

The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SATA Host AHCI IP Core for FPGA/ASIC

SATA Host AHCI IP Core for FPGA/ASIC

It can widely support systems that require a SATA host!

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC

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IP core "AndesCore N22"

IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N15/N15F"

IP core "AndesCore N15/N15F"

It is equipped with an IEEE-754 compliant floating-point unit that enhances floating-point processing capabilities!

The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D15/D15F"

IP core "AndesCore D15/D15F"

It comes with various configuration options such as MMU, cache, and local memory!

The "AndesCore D15/D15F" is a dual-issue superscalar AndesCore processor. Both processors are equipped with over 130 compiler-friendly general-purpose DSP and SIMD instructions to easily program DSP algorithms in C/C++. They are also designed for a variety of performance-driven applications in embedded Linux, real-time OS, or bare-metal environments. 【Specifications (partial)】 ■ Dual-issue pipeline ■ Over 130 DSP extension instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (D15F) *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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