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IP Cores(Core Core) - List of Manufacturers, Suppliers, Companies and Products

IP Cores Product List

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IP core "AndesCore A25MP"

IP core "AndesCore A25MP"

Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N13"

IP core "AndesCore N13"

With an 8-stage pipeline and a clock frequency exceeding 1GHz, the core delivers excellent performance of 2.05 DMIPS/MHz!

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N7"

IP core "AndesCore N7"

It is possible to reduce it to 12K gates! It serves as an ideal alternative to the 8051 and other 8-bit processor cores.

The "AndesCore N7" is an IP core that supports controllers requiring low power consumption, such as touch screens, storage, mobile devices, and sensors, as well as network connectivity needed for IoT devices. The ultra-low power consumption and small circuit size of the N7 are designed for SOC designs with performance constraints. FlashFetch technology can enhance the performance of latency-prone flash memory without additional power consumption. 【Specifications】 ■ Seamless transition from 8/16-bit MCUs to a complete 32-bit environment ■ Low power consumption to extend battery life ■ Small footprint with fewer gates and high code density ■ Speeding up Flash access and reducing power consumption with FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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