富士ソフト List of Products and Services

The "Agilex 3 SoC FPGA System on Module" is a product equipped with a dual-core Arm Cortex-A55 processor (up to 800MHz) and provides up to 135,110 logic elements. It features 4GB of HPS LPDDR4 memory (expandable up to 8GB), 32GB of eMMC storage (expandable up to 128GB), and 1Gb of QSPI flash (expandable up to 2Gb). Additionally, it offers four GTS transceivers (up to 12.5Gbps) and various interfaces (such as 2.5G Ethernet PHY, USB 2.0 OTG), and supports an operating temperature range of -40°C to +85°C. [Features (partial)] ■ AgilexTM 3 C-Series family with M16A Package ■ HPS LPDDR4 – 32bit 4GB (Expandable up to 8GB) *For more details, please download the PDF or feel free to contact us.

We would like to introduce the 'Agilex 7 SoC FPGA SOM iW-RainboW-G43M' that we handle. It features an enhanced 200G (half-duplex communication) encryption core with MACsec IP supporting AES-GCM encryption/decryption, protecting network traffic. With enhanced bfloat16 and up to 25 TFLOPS of digital signal processing (DSP) performance (FP16), it achieves high performance per watt. 【Features (partial)】 ■ Quad ARM Cortex A53 Processor ■ R31B/R31C Package With 4 x F-Tile ■ 32GB eMMC (Expandable) ■ 8GB DDR4 with ECC for HPS (64bit + 8bit) ■ 2 x 8GB DDR4 with ECC for FPGA (64bit + 8bit) *For more details, please download the PDF or feel free to contact us.

With extensive knowledge in hardware design centered around FPGAs, we can accommodate a wide range of FPGA development from small to large scale. We offer a one-stop solution that includes not only RTL design and other logical designs but also software development and custom implementation, including board development. We have formed alliances with various chip vendors, enabling us to work with not only major FPGA vendors but also new FPGA vendors that have gained attention due to the recent semiconductor supply shortages. 【Areas of Expertise】 - Research and Development - System Design - Hardware Development - Comprehensive Verification - System Verification - Mass Production

At Fujisoft, we offer the "Edge AI Consultation" service, which supports and provides the first step of POC (Proof of Concept) from initial consideration to data collection and implementation. 【Service】 The development of Edge AI can be broadly divided into two stages: the preliminary stage, which involves the design of objectives and the creation of training data, and the latter stage, which consists of AI training and its implementation as Edge AI. Our "Edge AI Consultation" service supports appropriate tasks and suitable choices at each stage with the help of our AI engineers and embedded engineers, enabling effective AI development for our customers. <Content> - Edge AI Data Consultation We support the creation of high-quality training data from the initial consideration stage. - Edge AI Implementation Consultation We support the implementation from AI creation to Edge device deployment. *For more details, please feel free to contact us.

We would like to introduce the 'Agilex 5 SoC FPGA SOM iW-RainboW-G58M' that we handle. It achieves excellent power efficiency performance with 1.6 times the performance per watt compared to competing products with 16nm FPGA, improving HPS energy efficiency with the first asymmetric Arm application processor cluster. With a wide range of IP sets and connection options covering a broad density range (50KLE-656KLE), it meets the diverse application needs and allows scaling of device size to accommodate various I/O standards for edge and embedded sensors that can be configured with a single FPGA device. [Features (partial)] ■ Agilex 5 E-Series family with B32A Package ■ Dual-core 64-bit Arm Cortex-A76 up to 1.8 GHz ■ Dual-core 64-bit Arm Cortex-A55 up to 1.5 GHz *For more details, please download the PDF or feel free to contact us.

Providing a group of MPEG standard codecs as IP Cores with high quality, low latency, low power consumption, and a small footprint. Available in Intel FPGA and Xilinx versions.

IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*

Northwest Logic has been providing controller IP cores focused on memory interfaces, MIPI, and PCI Express since its establishment in 1995. For memory interfaces, we offer a wide range of controllers including HBM2, DDR4/3, and LPDDR4, as well as CSI-2 and DSI-2/DSI for MIPI, and Gen4/3 for PCI Express. Our customizable IP cores are equipped with the full functionality of each protocol and are compatible with both ASIC and FPGA platforms. In addition to achieving high performance and quality for standalone controller IP cores through extensive simulation and hardware verification, we also focus on collaboration with PHY IP vendors and verification IP vendors, enabling us to provide total solutions for customers looking to integrate memory interfaces, MIPI, and PCI Express functionalities into their systems. *For more details, please refer to the PDF materials or feel free to contact us.

We specialize in acceleration boards and COTS boards targeted at applications that perform network packet processing (NPP), high-performance computing (HPC), and large-scale, high-volume signal processing (SP). Our product lineup includes boards equipped with Xilinx FPGAs and Intel(R)(Altera) FPGAs, providing platforms suitable for acceleration, security, and network development. We also offer PCI interfaces in various sizes. *For more details, please refer to the PDF materials or feel free to contact us.*

The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

The "IP Core for SATA RAID for FPGA/ASIC" provides RAID 0 (striping and concatenation) and splits data across multiple storage endpoints to achieve higher system storage performance. It is designed to operate with extremely low latency during data transfers between SATA storage devices and backend data interfaces. This can be used for RAID 0 storage solutions that require high speed and large capacity. 【Specifications (excerpt)】 - Supports RAID 0 (striping and concatenation) - Operates with an even number of drives - SATA transfer rates: 1.5Gbps, 3.0Gbps, and 6.0Gbps (supports automatic speed negotiation) *For more details, please download the PDF or feel free to contact us.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

We would like to introduce our "SATA Host APP IP Core for FPGA and ASIC." This is an IP core for SATA hosts that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It consists of the PHY layer, LNK layer, TRN (Transport) layer, application layer, SerDes, and FIFO interface. 【Specifications】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Uses FIFO for the DATA interface ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

The XUP-VV8 is a 3/4 length PCIe card equipped with a QSFP-DD (double-density) cage. The Virtex UltraScale + VU13P or VU9P FPGA supports up to 8x100GbE or 32x10/25GbE. The FPGA provides a large logic and memory resource with up to 3.8M logic cells and 455Mb of memory. This board also includes a jitter cleaner to support synchronous Ethernet. It can be configured as a single width for users who do not require DIMMs for external memory.

The XUP-P3R is a 3/4-length PCIe x16 card based on the Xilinx Virtex UltraScale+ FPGA. UltraScale+ devices provide high performance, high bandwidth, and low latency for systems that require large data flows and packet processing. This board offers up to 512 GBytes of memory, advanced clocking, extensive memory configurations, and four front panel QSFP cages that support up to 100 Gbps (4x25), including 100GbE. It also incorporates a Board Management Controller (BMC) for advanced system monitoring, significantly simplifying platform integration and management.