富士ソフト List of Products and Services

The "AndesCore E8" is a power-efficient and compact embedded controller enabled by the unique Andes Custom Extension (ACE). With its proprietary ACE environment, designers can specify architectural elements suitable for IoT applications. Using Andes' Custom-Optimized Instruction Development Tools (COPILOT), designers can create custom instructions that differentiate their products and designs from competing products based on standard instruction set processors. 【Specifications】 ■ Class-leading performance per MHz ■ Andes Custom Extension (ACE) significantly improves performance efficiency ■ Small footprint with fewer gates and high code density ■ Faster flash access and reduced power consumption through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N8" is an IP core that provides a long-term roadmap for customers requiring an upgrade path from 8-bit cores. With the ability to process both 16-bit and 32-bit instructions, it enables a reduction in the ROM size of program data. While being a computing platform comparable to an 8-bit controller, it achieves the performance of an advanced 32-bit processor. 【Specifications】 ■ Excellent overall performance ■ Vector interrupts for low-latency interrupt handling ■ Small footprint with fewer gates and high code density ■ Faster Flash access and power reduction through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N7" is an IP core that supports controllers requiring low power consumption, such as touch screens, storage, mobile devices, and sensors, as well as network connectivity needed for IoT devices. The ultra-low power consumption and small circuit size of the N7 are designed for SOC designs with performance constraints. FlashFetch technology can enhance the performance of latency-prone flash memory without additional power consumption. 【Specifications】 ■ Seamless transition from 8/16-bit MCUs to a complete 32-bit environment ■ Low power consumption to extend battery life ■ Small footprint with fewer gates and high code density ■ Speeding up Flash access and reducing power consumption with FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

The "AndesCore D15/D15F" is a dual-issue superscalar AndesCore processor. Both processors are equipped with over 130 compiler-friendly general-purpose DSP and SIMD instructions to easily program DSP algorithms in C/C++. They are also designed for a variety of performance-driven applications in embedded Linux, real-time OS, or bare-metal environments. 【Specifications (partial)】 ■ Dual-issue pipeline ■ Over 130 DSP extension instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (D15F) *For more details, please refer to the related links or feel free to contact us.

IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*

The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

Northwest Logic has been providing controller IP cores focused on memory interfaces, MIPI, and PCI Express since its establishment in 1995. For memory interfaces, we offer a wide range of controllers including HBM2, DDR4/3, and LPDDR4, as well as CSI-2 and DSI-2/DSI for MIPI, and Gen4/3 for PCI Express. Our customizable IP cores are equipped with the full functionality of each protocol and are compatible with both ASIC and FPGA platforms. In addition to achieving high performance and quality for standalone controller IP cores through extensive simulation and hardware verification, we also focus on collaboration with PHY IP vendors and verification IP vendors, enabling us to provide total solutions for customers looking to integrate memory interfaces, MIPI, and PCI Express functionalities into their systems. *For more details, please refer to the PDF materials or feel free to contact us.

Providing a group of MPEG standard codecs as IP Cores with high quality, low latency, low power consumption, and a small footprint. Available in Intel FPGA and Xilinx versions.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

We would like to introduce our "SATA Host APP IP Core for FPGA and ASIC." This is an IP core for SATA hosts that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It consists of the PHY layer, LNK layer, TRN (Transport) layer, application layer, SerDes, and FIFO interface. 【Specifications】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Uses FIFO for the DATA interface ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

The "IP Core for SATA RAID for FPGA/ASIC" provides RAID 0 (striping and concatenation) and splits data across multiple storage endpoints to achieve higher system storage performance. It is designed to operate with extremely low latency during data transfers between SATA storage devices and backend data interfaces. This can be used for RAID 0 storage solutions that require high speed and large capacity. 【Specifications (excerpt)】 - Supports RAID 0 (striping and concatenation) - Operates with an even number of drives - SATA transfer rates: 1.5Gbps, 3.0Gbps, and 6.0Gbps (supports automatic speed negotiation) *For more details, please download the PDF or feel free to contact us.

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

The "Agilex 3 SoC FPGA System on Module" is a product equipped with a dual-core Arm Cortex-A55 processor (up to 800MHz) and provides up to 135,110 logic elements. It features 4GB of HPS LPDDR4 memory (expandable up to 8GB), 32GB of eMMC storage (expandable up to 128GB), and 1Gb of QSPI flash (expandable up to 2Gb). Additionally, it offers four GTS transceivers (up to 12.5Gbps) and various interfaces (such as 2.5G Ethernet PHY, USB 2.0 OTG), and supports an operating temperature range of -40°C to +85°C. [Features (partial)] ■ AgilexTM 3 C-Series family with M16A Package ■ HPS LPDDR4 – 32bit 4GB (Expandable up to 8GB) *For more details, please download the PDF or feel free to contact us.

We would like to introduce the 'Agilex 7 SoC FPGA SOM iW-RainboW-G43M' that we handle. It features an enhanced 200G (half-duplex communication) encryption core with MACsec IP supporting AES-GCM encryption/decryption, protecting network traffic. With enhanced bfloat16 and up to 25 TFLOPS of digital signal processing (DSP) performance (FP16), it achieves high performance per watt. 【Features (partial)】 ■ Quad ARM Cortex A53 Processor ■ R31B/R31C Package With 4 x F-Tile ■ 32GB eMMC (Expandable) ■ 8GB DDR4 with ECC for HPS (64bit + 8bit) ■ 2 x 8GB DDR4 with ECC for FPGA (64bit + 8bit) *For more details, please download the PDF or feel free to contact us.

With extensive knowledge in hardware design centered around FPGAs, we can accommodate a wide range of FPGA development from small to large scale. We offer a one-stop solution that includes not only RTL design and other logical designs but also software development and custom implementation, including board development. We have formed alliances with various chip vendors, enabling us to work with not only major FPGA vendors but also new FPGA vendors that have gained attention due to the recent semiconductor supply shortages. 【Areas of Expertise】 - Research and Development - System Design - Hardware Development - Comprehensive Verification - System Verification - Mass Production

At Fujisoft, we offer the "Edge AI Consultation" service, which supports and provides the first step of POC (Proof of Concept) from initial consideration to data collection and implementation. 【Service】 The development of Edge AI can be broadly divided into two stages: the preliminary stage, which involves the design of objectives and the creation of training data, and the latter stage, which consists of AI training and its implementation as Edge AI. Our "Edge AI Consultation" service supports appropriate tasks and suitable choices at each stage with the help of our AI engineers and embedded engineers, enabling effective AI development for our customers. <Content> - Edge AI Data Consultation We support the creation of high-quality training data from the initial consideration stage. - Edge AI Implementation Consultation We support the implementation from AI creation to Edge device deployment. *For more details, please feel free to contact us.

We would like to introduce the 'Agilex 5 SoC FPGA SOM iW-RainboW-G58M' that we handle. It achieves excellent power efficiency performance with 1.6 times the performance per watt compared to competing products with 16nm FPGA, improving HPS energy efficiency with the first asymmetric Arm application processor cluster. With a wide range of IP sets and connection options covering a broad density range (50KLE-656KLE), it meets the diverse application needs and allows scaling of device size to accommodate various I/O standards for edge and embedded sensors that can be configured with a single FPGA device. [Features (partial)] ■ Agilex 5 E-Series family with B32A Package ■ Dual-core 64-bit Arm Cortex-A76 up to 1.8 GHz ■ Dual-core 64-bit Arm Cortex-A55 up to 1.5 GHz *For more details, please download the PDF or feel free to contact us.

We specialize in acceleration boards and COTS boards targeted at applications that perform network packet processing (NPP), high-performance computing (HPC), and large-scale, high-volume signal processing (SP). Our product lineup includes boards equipped with Xilinx FPGAs and Intel(R)(Altera) FPGAs, providing platforms suitable for acceleration, security, and network development. We also offer PCI interfaces in various sizes. *For more details, please refer to the PDF materials or feel free to contact us.*

The XUP-VV8 is a 3/4 length PCIe card equipped with a QSFP-DD (double-density) cage. The Virtex UltraScale + VU13P or VU9P FPGA supports up to 8x100GbE or 32x10/25GbE. The FPGA provides a large logic and memory resource with up to 3.8M logic cells and 455Mb of memory. This board also includes a jitter cleaner to support synchronous Ethernet. It can be configured as a single width for users who do not require DIMMs for external memory.

The XUP-P3R is a 3/4-length PCIe x16 card based on the Xilinx Virtex UltraScale+ FPGA. UltraScale+ devices provide high performance, high bandwidth, and low latency for systems that require large data flows and packet processing. This board offers up to 512 GBytes of memory, advanced clocking, extensive memory configurations, and four front panel QSFP cages that support up to 100 Gbps (4x25), including 100GbE. It also incorporates a Board Management Controller (BMC) for advanced system monitoring, significantly simplifying platform integration and management.

We would like to introduce the "Post-Quantum Cryptography IP Core" that we handle. Quantum computers are capable of quickly breaking current asymmetric encryption, putting important data and assets at risk. This solution provides a hardware-level security solution that protects data and hardware from quantum computer attacks by using algorithms selected by NIST and CNSA. 【Specifications (Excerpt)】 ■QSE-IP-86: Standalone engine that enables the acceleration of post-quantum cryptography ■QSE-IP-86-DPA: Standalone engine that provides acceleration of post-quantum cryptography and a DPA-resistant cryptographic accelerator ■CryptoManager RT-634: Programmable root of trust that enables the acceleration of post-quantum cryptography ■CryptoManager RT-664: Programmable root of trust equipped with acceleration of post-quantum cryptography, DPA resistance, and FIA-protected cryptographic accelerator *For more details, please refer to the related links or feel free to contact us.

Rambus' "Quantum Safe Engine (QSE) IP" is a product that provides acceleration for post-quantum cryptography for ASIC, SoC, and FPGA devices. This product is integrated into hardware Root of Trust or embedded secure elements, combined with the PKE-IP-85 core that accelerates classical public key cryptography and the TRNG-IP-76 core that generates true random numbers. For high-security applications that require additional protection against Differential Power Analysis (DPA) attacks, a DPA-resistant version of QSE is available. 【Features】 ■ Compliant with FIPS 203 ML-KEM and FIPS 204 ML-DSA standards ■ NIST CAVP (used in FIPS 140-3 compliant products) ■ Utilizes quantum-resistant algorithms CRYSTALS-Kyber and CRYSTALS-Dilithium ■ Includes acceleration for SHA-3, SHAKE-128, and SHAKE-256 *For more details, please refer to the related links or feel free to contact us.

This product is a fully programmable hardware security core compliant with FIPS 140-3, designed from the ground up to provide quantum-resistant security for data centers and other applications requiring advanced security. Device and system architects are facing increasingly diverse security threats, including the risks posed by quantum computers. The need for hardware-based Root of Trust security implementations remains constant across various applications. This product offers extensive protection against both hardware and software attacks through advanced side-channel attack countermeasures, tamper resistance technologies, and security techniques. 【Features】 ■ Supports various security certifications up to Level 3 ■ Provides a future-proof hardware security solution ■ Enables the development of secure and reliable applications ■ Allows for the configuration of independent authorities and access levels *For more details, please refer to the related links or feel free to contact us.

The "Quantum Safe IPsec Toolkit (QuickSec Quantum)" is a complete IPsec software implementation that supports Quantum Safe encryption. Quantum Safe encryption is designed to withstand attacks from quantum computers and is an essential feature for cutting-edge security products. The Quantum Safe IPsec Toolkit builds on the achievements, experience, and performance of the Rambus Classic IPsec Toolkit, leading IPsec into the era of quantum safety. 【Features】 ■ High session setup speed ■ High availability (HA) ■ Easy debugging ■ Multi-tenant ■ General-purpose data plane API *For more details, please refer to the related links or feel free to contact us.

"DOSPI" is an innovative octal SPI designed to provide very fast operation for SPI memory. It has sufficient flexibility to connect directly to many standard products from multiple manufacturers. Furthermore, the IP core supports common 8, 16, and 32-bit processors. Please feel free to contact us when you need assistance. 【Specifications (Partial)】 ■ Operates with 8, 16, and 32-bit CPUs ■ Full-duplex synchronous serial data transfer ■ DMA support ■ Support for 32, 16, and 8-bit systems ■ Support for various system bus standards *For more details, please download the PDF (English version) or feel free to contact us.

"DQSPI" is an innovative Quad SPI designed to provide very fast operation for SPI memory. It offers the flexibility to connect with standard peripheral products from various manufacturers. Additionally, the IP core supports common 8, 16, and 32-bit processors. Please feel free to contact us if you have any inquiries. 【Specifications (partial)】 ■ Operates with 8, 16, and 32-bit CPUs ■ Full-duplex synchronous serial data transfer ■ DMA support ■ Supports 32, 16, and 8-bit systems ■ Support for various system bus standard specifications *For more details, please download the PDF (English version) or feel free to contact us.

The "DSPI" is a fully configurable SPI master/slave device. Users can set the polarity and phase of the serial clock signal SCK. This not only enables the microcontroller to communicate with serial peripheral devices but also allows communication with inter-processors in a multi-master system. 【Features】 <SPI Master> ■ Master and multi-master operation ■ 8 SPI slave select lines ■ System error detection ■ Mode fault error ■ Write collision error *For more details, please download the PDF (English version) or feel free to contact us.

The "D16550" is a soft core universal asynchronous receiver/transmitter (UART) that is functionally the same as the TL16C550A. It supports serial transmission in two modes: UART and FIFO. In FIFO mode, an internal FIFO is activated, storing 16 bytes (with 3 bits of error data per byte in the RCVR FIFO) in both the receive and transmit directions. Additionally, it features a programmable 16-bit baud rate generator that can divide the timing reference clock input by a divisor ranging from 1 to (2^16-1). 【Specifications (partial)】 ■ Software compatible with 16450 and 16550 UART ■ Configuration features ■ Isolated configurable BAUD clock line ■ Majority logic ■ Supports RS232 and RS485 *For more details, please download the PDF (English version) or feel free to contact us.