アルデック・ジャパン List of News Articles

The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standard, how it will be implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. In this webinar, we will demonstrate the use of ALINT-PRO to enforce coding standards and highlight the benefits of streamlining the overall design review to meet the objectives of DO-254.

Although I have heard that verification efficiency at the RTL stage improves with verification methodologies using SystemVerilog such as UVM, many designers may not fully understand what can be done with SystemVerilog and how to use it. In this seminar, we will introduce the basic functions and usefulness of SystemVerilog verification using a sample design. 1. Design Overview 2. UART Test Environment 3. Assertions (SVA & PSL) 4. Functional Coverage 5. Random Test Bench 6. DPI-C

In today's large-scale ASIC/FPGA design, clock domain crossing verification is one of the important tasks. Many designs include a large number of third-party IPs, and their source code may be encrypted or non-encrypted. It is crucial to perform clock domain crossing verification for designs that include such encrypted IPs, which necessitates the preparation of an abstraction model for encrypted IP cores. Furthermore, as the design scale increases, it becomes impractical to analyze the entire system at once. It is more reasonable to verify individual leap design modules using a partitioned analysis approach and to abstract the verified modules when performing system-level analysis. This webinar will introduce the development method of abstraction models for encrypted IPs and how to analyze large-scale designs using the abstracted leap design module models.

Requirements-based verification is a common verification process for FPGA designs used in safety-critical systems. The effectiveness of requirements-based verification depends on the quality and accuracy of the requirements. Verification methods such as constraint-based random verification using assertion-based verification help identify ambiguous or incomplete requirements early in the design and verification process. Additionally, assertions can enhance the observability of the design, significantly reducing debugging time. This increases the time available for exploring new bugs, leading to improved verification quality. In this webinar, we will introduce how to optimize and verify requirements using SystemVerilog assertions.

ALINT-PRO provides a powerful means for static analysis and verification of clock domain crossing (CDC). It detects and verifies clock trees and clock domains, applying topological pattern matching techniques to validate the design structure over clock domain crossings. However, to ensure that there are no CDC-related issues, it is necessary to add dynamic CDC verification using a simulator in addition to static CDC verification. ALINT-PRO can enhance functional verification by generating check code for CDC points with its assertion generation engine. In this webinar, we will introduce a complete clock domain crossing verification methodology, from static verification using ALINT-PRO to dynamic verification using Riviera-PRO.

Constraint random and functional coverage using SystemVerilog are widely used by many designers, but the simulators that support these features tend to be expensive products. Cocotb, which uses Python as a verification language, makes it easy to utilize these features and provides designers who have not been able to try them with an opportunity to challenge new verification methods. In this webinar, we will introduce two approaches for using constraint random and functional coverage with cocotb.

In safety-critical design control logic, finite state machines (FSM) are an important component. When the FPGA within the system is operating, external factors such as single event upsets or radiation can cause the bit values stored in the FSM registers to change to incorrect values in a nondeterministic manner, potentially leading to system malfunctions or failures. Furthermore, with the miniaturization of transistors, this issue has become more common. In this webinar, we will introduce various methods for developing robust and safe FSMs, from best practices in FSM design to reliable FSM design techniques.

Typically, hardware designers are very busy and have little time to try out new methodologies. Unfortunately, the official documentation for UVM (Universal Verification Methodology) is written by verification engineers for verification engineers, focusing on high-level functionality while ignoring lower-level details such as connecting the UVM testbench to the design. In this webinar, we will explain the main UVM components such as Sequencer and Driver using a simple design and virtual interfaces.

If issues in RTL coding are not detected early, it can lead to costly design iterations and unexpected failures later in the development cycle. Lint (DRC) tools are powerful static analysis methods that detect bugs, inefficiencies, and structural problems in RTL code. Lint tools analyze HDL code against hundreds of industry-proven design rules regarding syntax, naming conventions, synthesizability, and performance optimization, and they also help identify issues related to clock domain crossing (CDC), reset tree problems, and mismatches between RTL and synthesis. In this webinar, we will explain the main advantages of lint tools using real examples and introduce how linting can improve code quality, enhance design reusability, and prevent unexpected situations in later stages.

Cocotb is a coroutine-based co-simulation testbench environment for verifying VHDL and SystemVerilog/Verilog designs using Python. It is an open-source environment hosted on GitHub. It uses the same concepts of reusability and functional verification as UVM, but is implemented in Python. This webinar will provide an overview of cocotb.

It has become clear that with today's large-scale ASICs/SoCs and FPGAs, traditional RTL modeling techniques alone make design and verification difficult. As a result, the concept of Transaction Level Modeling (TLM) has been widely adopted, and it has become essential in verification methods such as UVM. In this webinar, we will introduce TLM using terminology explanations and implementation examples with simple sample designs.

Typically, in simulations, waveforms are visually checked, but confirming dozens to hundreds of cycles is a very labor-intensive task. By using assertions to monitor and check the behavior of the design, the burden on designers can be reduced. In this webinar, we will introduce assertion languages, libraries, and methods of description.

In ASIC design verification, various types of coverage are very important as verification completion criteria, but in FPGA design verification, physical verification has been emphasized, and coverage is often not collected. However, in the current trend of large-scale and complex FPGA design verification, functional verification before physical verification plays a very important role. Additionally, coverage can range from simple types like statement and branch coverage to more complex types like Covergroups that include assertions and constrained random tests. In this webinar, we will introduce code coverage and functional coverage, as well as various aspects related to coverage such as test plans and test rankings.

～ Understanding SystemVerilog Objects ～ Many hardware designers use RTL design techniques for the development of various applications. However, the verification of large-scale designs requires higher levels of abstraction, such as functional coverage, constrained random, and UVM. To achieve this, object-oriented programming (OOP) is essential, but hardware designers often have limited opportunities and time to engage with it. In this seminar, we will introduce SystemVerilog classes and object-oriented programming using simple examples.

With the evolution of FPGA technology, the traditional programmable logic domain has expanded to include CPUs, GPUs, and high-speed peripherals, making design verification increasingly difficult. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this final installment of the webinar series, we will introduce advanced verification solutions such as scoreboards, checkers, functional coverage, and assertions. We will also cover transaction-based debugging and unit linting features, as well as regression testing using Riviera-PRO.

Although I have heard that verification efficiency at the RTL stage improves with verification methodologies using SystemVerilog such as UVM, many designers may not fully understand what can be done with SystemVerilog and how to use it. In this seminar, we will introduce the basic functions and usefulness of SystemVerilog for verification using sample designs. 1. Design Overview 2. UART Test Environment 3. Assertions (SVA & PSL) 4. Functional Coverage 5. Random Test Bench 6. DPI-C