アルデック・ジャパン List of News Articles

The RTCA/DO-254, published in 2000, serves as a guideline for the development of airborne electronic equipment equipped with FPGA/ASIC according to standards; however, in recent designs, its content has become outdated. EASA and FAA have aimed to harmonize compliance standards, and at the same time, issued AMC 20-152A/AC 20-152A as new objectives that DO-254 applicants should meet. This webinar will introduce an overview of this new document, as well as discuss its impact on the design and verification processes of airborne electronic equipment and appropriate tools for streamlining these processes.

UVM (Universal Verification Methodology) is one of the verification methods that enables advanced verification flows for ASICs and large-scale FPGAs. However, writing UVM from scratch is a complex and time-consuming task. The UVM generator in Riviera-PRO reduces complexity by automatically generating SystemVerilog templates for UVM test benches and simulation scripts for designs written in VHDL, Verilog/SystemVerilog, rather than starting from scratch. This webinar will focus on how to use the UVM generator and the benefits it brings to users who create UVM code from scratch.

As FPGA designs become larger and more complex, the importance of clock domain crossing (CDC) verification is increasingly emphasized. Improper handling of asynchronous clock boundaries can lead to metastability, glitches, and loss of data integrity, potentially causing unpredictable behavior in hardware. The AMD (Xilinx) Vivado Design Suite includes built-in CDC checking features, but these may be insufficient for complex multi-asynchronous clock designs. While Vivado's CDC report feature provides useful information through Xilinx-specific checks such as the ASYNC_REG attribute, it does not match the detailed analytical capabilities of dedicated CDC verification tools like ALINT-PRO. In this webinar, we will compare Vivado's built-in CDC verification capabilities with the advanced features of ALINT-PRO, highlighting CDC issues that may be overlooked in Vivado and demonstrating how ALINT-PRO can enhance CDC analysis and debugging.

The Open Verification Library (OVL) provided by Accelera offers designers a way to easily perform assertion-based verification. OVL supports commonly used design languages (VHDL, Verilog, SystemVerilog) and can be used not only for simulation but also for formal verification and emulation. In this webinar, we will explain OVL while presenting code examples.

The complex port connections in traditional Verilog HDL are prone to becoming breeding grounds for bugs and contribute to reduced code visibility. By introducing SystemVerilog's Interface, we can encapsulate hundreds of signal lines into a single object, dramatically improving design and verification productivity. In this webinar, we will introduce the basics of the Interface feature, which simplifies signal connections and enhances code readability and reusability, along with practical examples of its application to test benches. Let's break free from spaghetti code between modules and adopt a smarter design and verification style!

Constraint random and functional coverage using SystemVerilog are utilized by many designers, but the simulators that support these features tend to be expensive products. Cocotb, which uses Python as a verification language, makes it easier to use these features and provides an opportunity for designers who have not been able to try them to challenge new verification methods. In this webinar, we will introduce two approaches to using constraint random and functional coverage with cocotb.

DO-254 specifies a rigorous and requirements-based process for FPGA design development that emphasizes safety, reliability, and compliance with regulations. This process includes key steps such as defining verifiable requirements, developing design elements with ensured traceability, creating high-quality RTL code, and conducting comprehensive verification. Each phase is essential for preventing hardware failures and achieving robust designs. In this webinar, we will introduce the processes necessary to achieve compliance with DO-254 in aircraft-mounted FPGA design. Additionally, we will also present tools and methods for optimizing the design and verification workflow.

Understanding TLM Overview It has become increasingly clear that traditional RTL modeling techniques alone are insufficient for the design and verification of large-scale ASICs/SoCs and FPGAs. As a result, the concept of Transaction Level Modeling (TLM) has been widely adopted, and it has become essential in verification methodologies such as UVM. In this webinar, we will introduce TLM using terminology explanations and implementation examples with simple sample designs.

Code coverage and functional coverage are widely used to evaluate the comprehensiveness of verification. However, improving coverage requires a vast number of test benches and stimuli. Traditional direct testing is easy to use for checking the functions to be verified, but it cannot test for unexpected content. Additionally, conventional simple random testing may generate unnecessary stimuli. SystemVerilog's constrained random feature allows for the control of random number generation through constraints, enabling the generation of diverse stimuli within a single test bench. This results in improved coverage rates with minimal test bench descriptions. In this webinar, we will introduce techniques related to the description and constraints of SystemVerilog's constrained random feature.

The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standards, how they are implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. This webinar will demonstrate the benefits of using ALINT-PRO to enforce coding standards and streamline the overall design review to meet the objectives of DO-254.

The traditional paper-based requirements (specifications) for design coding by design teams and individuals have significantly impacted the quality of design, depending on the understanding of the requirements and the experience of the designers. Therefore, Model-Based Design (MBD) has gained attention as a means to improve development efficiency and quality. In MBD, MATLAB/Simulink from MathWorks is widely used as a tool. Aldec's simulator provides a cooperative verification interface with MATLAB/Simulink, allowing you to use the following verification environments: - Simulink cooperative verification by placing HDL blocks on Simulink diagrams - MATLAB direct interface using MATLAB files (.m files) from HDL test benches In this webinar, we will explain how to use the MATLAB/Simulink cooperative verification interface and the flow from simulation to result verification.

This webinar is aimed at those interested in CDC (Clock Domain Crossing) verification in FPGA design, and will cover the following topics: * What are CDC issues? * General approaches and precautions * Considerations for synchronizers in FPGA design * Solutions for CDC verification Additionally, for those interested, we will provide a one-month evaluation license for ALINT-PRO, a CDC/RDC verification solution offered by Aldec. We will also assist with the execution of the verification. If you have struggled with CDC issues in the past or are looking to start CDC verification, please join us.

Code coverage is the most commonly used effective method to verify the comprehensiveness of verification. However, coverage such as topological paths cannot be guaranteed. Functional coverage is a coverage method provided by SystemVerilog, which serves as a user-defined metric to measure the comprehensiveness of design specifications verified through simulation execution. It is measured using SystemVerilog assertions and Covergroup descriptions for the design features listed in the verification plan and is used for advanced verification of complex designs. In this webinar, we will introduce SystemVerilog's functional coverage and discuss techniques for its description.

Recent hardware design has seen an increase in scale and complexity, which may lead to prolonged design verification processes. In this context, there is growing attention on cleaning up design code before design verification. Cleanup can be performed relatively quickly and significantly reduces the time and effort required for design verification. Additionally, as SystemVerilog (design) becomes more prevalent in hardware design, the importance of checking design code using these tools is also increasing. ALINT-PRO can statically verify most common SystemVerilog (design) elements, allowing for the early detection of critical design issues in the design cycle. In this webinar, we will introduce the issues related to SystemVerilog and the rules for checking them.

The AXI4 Stream protocol is used as a standard interface for exchanging data between connected IPs within FPGA designs. When crossing clock domains, the AXI4 Stream interconnect is based on a switch that can transfer data to another asynchronous clock domain. The ALDEC_CDC rule plugin includes numerous rules for checking design quality, design constraints, and clock and reset trees. It is used for verifying the synchronous circuits of the design. However, static CDC verification methods alone may not guarantee the completeness of CDC verification tasks, making dynamic CDC verification essential. The main techniques for dynamic CDC verification include checks using CDC assertions and modeling random delay insertion during clock domain crossing. In this webinar, both static and dynamic verification methods for CDC verification of AXI4 Stream-based IP will be introduced, and the design and usage of CDC assertions automatically generated from ALINT-PRO, along with synchronizer models equipped with random delay insertion, will be explained.

Many hardware designers use RTL design methodologies for the development of various applications. However, verification of large-scale designs requires higher levels of abstraction, such as functional coverage, constrained random, and UVM. To achieve this, object-oriented programming (OOP) is essential, but hardware designers often have limited opportunities and time to engage with it. In this seminar, we will introduce SystemVerilog classes and object-oriented programming using simple examples.

Henderson, NV – January 14, 2026 – Aldec, Inc., a pioneer in mixed HDL language simulation and verification solutions for FPGA and ASIC design, today announced the release of ALINT-PRO 2025.12, which provides new design rules and guidance for mixed-language projects. This update will help engineering teams improve accuracy, maintainability, and IP interoperability when combining VHDL and Verilog/SystemVerilog within a single project. As mixed-language development becomes common for IP reuse, third-party integration, and long-term product maintenance, design teams face challenges caused by ambiguous mappings, inconsistent parameter passing, and misuse of configurations. ALINT-PRO 2025.12 reduces these risks by applying a concentrated set of best practice rules aimed at preventing integration issues before simulation, logic synthesis, and downstream verification. Please refer to the attached document for more details.