アルデック・ジャパン Company Overview

The traditional paper-based requirements (specifications) for design coding by design teams and individuals have significantly impacted the quality of design, depending on the understanding of the requirements and the experience of the designers. Therefore, Model-Based Design (MBD) has gained attention as a means to improve development efficiency and quality. In MBD, MATLAB/Simulink from MathWorks is widely used as a tool. Aldec's simulator provides a cooperative verification interface with MATLAB/Simulink, allowing you to use the following verification environments: - Simulink cooperative verification by placing HDL blocks on Simulink diagrams - MATLAB direct interface using MATLAB files (.m files) from HDL test benches In this webinar, we will explain how to use the MATLAB/Simulink cooperative verification interface and the flow from simulation to result verification.

This webinar is aimed at those interested in CDC (Clock Domain Crossing) verification in FPGA design, and will cover the following topics: * What are CDC issues? * General approaches and precautions * Considerations for synchronizers in FPGA design * Solutions for CDC verification Additionally, for those interested, we will provide a one-month evaluation license for ALINT-PRO, a CDC/RDC verification solution offered by Aldec. We will also assist with the execution of the verification. If you have struggled with CDC issues in the past or are looking to start CDC verification, please join us.

Recent hardware design has seen an increase in scale and complexity, which may lead to prolonged design verification processes. In this context, there is growing attention on cleaning up design code before design verification. Cleanup can be performed relatively quickly and significantly reduces the time and effort required for design verification. Additionally, as SystemVerilog (design) becomes more prevalent in hardware design, the importance of checking design code using these tools is also increasing. ALINT-PRO can statically verify most common SystemVerilog (design) elements, allowing for the early detection of critical design issues in the design cycle. In this webinar, we will introduce the issues related to SystemVerilog and the rules for checking them.