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Recent hardware design has seen an increase in scale and complexity, which may lead to prolonged design verification processes. In this context, there is growing attention on cleaning up design code before design verification. Cleanup can be performed relatively quickly and significantly reduces the time and effort required for design verification. Additionally, as SystemVerilog (design) becomes more prevalent in hardware design, the importance of checking design code using these tools is also increasing. ALINT-PRO can statically verify most common SystemVerilog (design) elements, allowing for the early detection of critical design issues in the design cycle. In this webinar, we will introduce the issues related to SystemVerilog and the rules for checking them.

Code coverage is the most commonly used effective method to verify the comprehensiveness of verification. However, coverage such as topological paths cannot be guaranteed. Functional coverage is a coverage method provided by SystemVerilog, which serves as a user-defined metric to measure the comprehensiveness of design specifications verified through simulation execution. It is measured using SystemVerilog assertions and Covergroup descriptions for the design features listed in the verification plan and is used for advanced verification of complex designs. In this webinar, we will introduce SystemVerilog's functional coverage and discuss techniques for its description.

The AXI4 Stream protocol is used as a standard interface for exchanging data between connected IPs within FPGA designs. When crossing clock domains, the AXI4 Stream interconnect is based on a switch that can transfer data to another asynchronous clock domain. The ALDEC_CDC rule plugin includes numerous rules for checking design quality, design constraints, and clock and reset trees. It is used for verifying the synchronous circuits of the design. However, static CDC verification methods alone may not guarantee the completeness of CDC verification tasks, making dynamic CDC verification essential. The main techniques for dynamic CDC verification include checks using CDC assertions and modeling random delay insertion during clock domain crossing. In this webinar, both static and dynamic verification methods for CDC verification of AXI4 Stream-based IP will be introduced, and the design and usage of CDC assertions automatically generated from ALINT-PRO, along with synchronizer models equipped with random delay insertion, will be explained.