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The complex port connections in traditional Verilog HDL are prone to becoming breeding grounds for bugs and contribute to reduced code visibility. By introducing SystemVerilog's Interface, we can encapsulate hundreds of signal lines into a single object, dramatically improving design and verification productivity. In this webinar, we will introduce the basics of the Interface feature, which simplifies signal connections and enhances code readability and reusability, along with practical examples of its application to test benches. Let's break free from spaghetti code between modules and adopt a smarter design and verification style!

Constraint random and functional coverage using SystemVerilog are utilized by many designers, but the simulators that support these features tend to be expensive products. Cocotb, which uses Python as a verification language, makes it easier to use these features and provides an opportunity for designers who have not been able to try them to challenge new verification methods. In this webinar, we will introduce two approaches to using constraint random and functional coverage with cocotb.

DO-254 specifies a rigorous and requirements-based process for FPGA design development that emphasizes safety, reliability, and compliance with regulations. This process includes key steps such as defining verifiable requirements, developing design elements with ensured traceability, creating high-quality RTL code, and conducting comprehensive verification. Each phase is essential for preventing hardware failures and achieving robust designs. In this webinar, we will introduce the processes necessary to achieve compliance with DO-254 in aircraft-mounted FPGA design. Additionally, we will also present tools and methods for optimizing the design and verification workflow.