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Most FPGA designs include configurable IP blocks provided by FPGA vendors. These IP blocks may contain synthesizable RTL code. In CDC verification, pseudo violations can occur due to this IP, leading to increased analysis time. In this webinar, we will introduce how to describe constraints for IP using block-level constraints in ALINT-PRO.

With the evolution of FPGA technology, traditional programmable logic areas have been supplemented by CPUs, GPUs, and high-speed peripherals, making design verification increasingly challenging. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this final installment of the webinar series, we will introduce advanced verification solutions such as scoreboards, checkers, functional coverage, and assertions. We will also cover transaction-based debugging and unit linting features, as well as regression testing using Riviera-PRO.

In high-speed FPGA design, not only high clock frequencies are required, but also carefully optimized RTL design. Advanced linting becomes a static RTL code analysis process that detects hidden issues in the code against hundreds of design rules. In addition to improving code quality, advanced linting directly contributes to performance optimization, which is a critical factor in achieving frequency, power consumption, and area targets for high-speed FPGA designs. ALINT-PRO helps designers identify and fix potential bottlenecks early in the design cycle, contributing to the reduction of time-consuming implementation and timing closure with FPGA vendor tools. This webinar will introduce how to apply and the effects of advanced linting using ALINT-PRO.