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The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standard, how it will be implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. In this webinar, we will demonstrate the use of ALINT-PRO to enforce coding standards and highlight the benefits of streamlining the overall design review to meet the objectives of DO-254.

Although I have heard that verification efficiency at the RTL stage improves with verification methodologies using SystemVerilog such as UVM, many designers may not fully understand what can be done with SystemVerilog and how to use it. In this seminar, we will introduce the basic functions and usefulness of SystemVerilog verification using a sample design. 1. Design Overview 2. UART Test Environment 3. Assertions (SVA & PSL) 4. Functional Coverage 5. Random Test Bench 6. DPI-C

In today's large-scale ASIC/FPGA design, clock domain crossing verification is one of the important tasks. Many designs include a large number of third-party IPs, and their source code may be encrypted or non-encrypted. It is crucial to perform clock domain crossing verification for designs that include such encrypted IPs, which necessitates the preparation of an abstraction model for encrypted IP cores. Furthermore, as the design scale increases, it becomes impractical to analyze the entire system at once. It is more reasonable to verify individual leap design modules using a partitioned analysis approach and to abstract the verified modules when performing system-level analysis. This webinar will introduce the development method of abstraction models for encrypted IPs and how to analyze large-scale designs using the abstracted leap design module models.