アルデック・ジャパン Company Profile

In high-speed FPGA design, not only high clock frequencies are required, but also carefully optimized RTL design. Advanced linting becomes a static RTL code analysis process that detects hidden issues in the code against hundreds of design rules. In addition to improving code quality, advanced linting directly contributes to performance optimization, which is a critical factor in achieving frequency, power consumption, and area targets for high-speed FPGA designs. ALINT-PRO helps designers identify and fix potential bottlenecks early in the design cycle, contributing to the reduction of time-consuming implementation and timing closure with FPGA vendor tools. This webinar will introduce how to apply and the effects of advanced linting using ALINT-PRO.

With the evolution of FPGA technology, traditional programmable logic domains have been supplemented by CPUs, GPUs, and high-speed peripherals, making design verification increasingly challenging. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this webinar, we will outline advanced simulation-based verification processes, FPGA-centric verification processes, and how to create verification plans, including what to verify and how to do so.

Section 6.2 "Verification Process" of RTCA/DO-254 stipulates the need to maintain and verify requirements from the RTL simulation stage to the hardware verification stage. This regulation makes it a very important task to conduct functional verification of digital designs on actual hardware in development based on DO-254. In this webinar, we will introduce examples of common challenges often encountered during hardware verification, and more importantly, solutions to overcome these challenges.