Free Webinar: A Shortcut to Building UVM Verification Environments
UVM (Universal Verification Methodology) is one of the verification methods that enables advanced verification flows for ASICs and large-scale FPGAs. However, writing UVM from scratch is a complex and time-consuming task. The UVM generator in Riviera-PRO reduces complexity by automatically generating SystemVerilog templates for UVM test benches and simulation scripts for designs written in VHDL, Verilog/SystemVerilog, rather than starting from scratch. This webinar will focus on how to use the UVM generator and the benefits it brings to users who create UVM code from scratch.

| Date and time | Wednesday, Nov 18, 2026 03:00 PM ~ 04:00 PM |
|---|---|
| Entry fee | Free |
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