Free Webinar: Assertion-Based Verification of Verilog and VHDL Designs Using OVL
The Open Verification Library (OVL) provided by Accelera offers designers a way to easily perform assertion-based verification. OVL supports commonly used design languages (VHDL, Verilog, SystemVerilog) and can be used not only for simulation but also for formal verification and emulation. In this webinar, we will explain OVL while presenting code examples.

| Date and time | Wednesday, Oct 21, 2026 03:00 PM ~ 04:00 PM |
|---|---|
| Entry fee | Free |
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