FPGA Development Integrated Environment Active-HDL

The Open Verification Library (OVL) provided by Accelera offers designers a way to easily perform assertion-based verification. OVL supports commonly used design languages (VHDL, Verilog, SystemVerilog) and can be used not only for simulation but also for formal verification and emulation. In this webinar, we will explain OVL while presenting code examples.

The complex port connections in traditional Verilog HDL are prone to becoming breeding grounds for bugs and contribute to reduced code visibility. By introducing SystemVerilog's Interface, we can encapsulate hundreds of signal lines into a single object, dramatically improving design and verification productivity. In this webinar, we will introduce the basics of the Interface feature, which simplifies signal connections and enhances code readability and reusability, along with practical examples of its application to test benches. Let's break free from spaghetti code between modules and adopt a smarter design and verification style!

DO-254 specifies a rigorous and requirements-based process for FPGA design development that emphasizes safety, reliability, and compliance with regulations. This process includes key steps such as defining verifiable requirements, developing design elements with ensured traceability, creating high-quality RTL code, and conducting comprehensive verification. Each phase is essential for preventing hardware failures and achieving robust designs. In this webinar, we will introduce the processes necessary to achieve compliance with DO-254 in aircraft-mounted FPGA design. Additionally, we will also present tools and methods for optimizing the design and verification workflow.

Understanding TLM Overview It has become increasingly clear that traditional RTL modeling techniques alone are insufficient for the design and verification of large-scale ASICs/SoCs and FPGAs. As a result, the concept of Transaction Level Modeling (TLM) has been widely adopted, and it has become essential in verification methodologies such as UVM. In this webinar, we will introduce TLM using terminology explanations and implementation examples with simple sample designs.