FPGA Development Integrated Environment Active-HDL

The traditional paper-based requirements (specifications) for design coding by design teams and individuals have significantly impacted the quality of design, depending on the understanding of the requirements and the experience of the designers. Therefore, Model-Based Design (MBD) has gained attention as a means to improve development efficiency and quality. In MBD, MATLAB/Simulink from MathWorks is widely used as a tool. Aldec's simulator provides a cooperative verification interface with MATLAB/Simulink, allowing you to use the following verification environments: - Simulink cooperative verification by placing HDL blocks on Simulink diagrams - MATLAB direct interface using MATLAB files (.m files) from HDL test benches In this webinar, we will explain how to use the MATLAB/Simulink cooperative verification interface and the flow from simulation to result verification.

Code coverage is the most commonly used effective method to verify the comprehensiveness of verification. However, coverage such as topological paths cannot be guaranteed. Functional coverage is a coverage method provided by SystemVerilog, which serves as a user-defined metric to measure the comprehensiveness of design specifications verified through simulation execution. It is measured using SystemVerilog assertions and Covergroup descriptions for the design features listed in the verification plan and is used for advanced verification of complex designs. In this webinar, we will introduce SystemVerilog's functional coverage and discuss techniques for its description.

The AXI4 Stream protocol is used as a standard interface for exchanging data between connected IPs within FPGA designs. When crossing clock domains, the AXI4 Stream interconnect is based on a switch that can transfer data to another asynchronous clock domain. The ALDEC_CDC rule plugin includes numerous rules for checking design quality, design constraints, and clock and reset trees. It is used for verifying the synchronous circuits of the design. However, static CDC verification methods alone may not guarantee the completeness of CDC verification tasks, making dynamic CDC verification essential. The main techniques for dynamic CDC verification include checks using CDC assertions and modeling random delay insertion during clock domain crossing. In this webinar, both static and dynamic verification methods for CDC verification of AXI4 Stream-based IP will be introduced, and the design and usage of CDC assertions automatically generated from ALINT-PRO, along with synchronizer models equipped with random delay insertion, will be explained.

Many hardware designers use RTL design methodologies for the development of various applications. However, verification of large-scale designs requires higher levels of abstraction, such as functional coverage, constrained random, and UVM. To achieve this, object-oriented programming (OOP) is essential, but hardware designers often have limited opportunities and time to engage with it. In this seminar, we will introduce SystemVerilog classes and object-oriented programming using simple examples.