FPGA Development Integrated Environment Active-HDL

DO-254 specifies a rigorous and requirements-based process for FPGA design development that emphasizes safety, reliability, and compliance with regulations. This process includes key steps such as defining verifiable requirements, developing design elements with ensured traceability, creating high-quality RTL code, and conducting comprehensive verification. Each phase is essential for preventing hardware failures and achieving robust designs. In this webinar, we will introduce the processes necessary to achieve compliance with DO-254 in aircraft-mounted FPGA design. Additionally, we will also present tools and methods for optimizing the design and verification workflow.

Understanding TLM Overview It has become increasingly clear that traditional RTL modeling techniques alone are insufficient for the design and verification of large-scale ASICs/SoCs and FPGAs. As a result, the concept of Transaction Level Modeling (TLM) has been widely adopted, and it has become essential in verification methodologies such as UVM. In this webinar, we will introduce TLM using terminology explanations and implementation examples with simple sample designs.

Code coverage and functional coverage are widely used to evaluate the comprehensiveness of verification. However, improving coverage requires a vast number of test benches and stimuli. Traditional direct testing is easy to use for checking the functions to be verified, but it cannot test for unexpected content. Additionally, conventional simple random testing may generate unnecessary stimuli. SystemVerilog's constrained random feature allows for the control of random number generation through constraints, enabling the generation of diverse stimuli within a single test bench. This results in improved coverage rates with minimal test bench descriptions. In this webinar, we will introduce techniques related to the description and constraints of SystemVerilog's constrained random feature.

The traditional paper-based requirements (specifications) for design coding by design teams and individuals have significantly impacted the quality of design, depending on the understanding of the requirements and the experience of the designers. Therefore, Model-Based Design (MBD) has gained attention as a means to improve development efficiency and quality. In MBD, MATLAB/Simulink from MathWorks is widely used as a tool. Aldec's simulator provides a cooperative verification interface with MATLAB/Simulink, allowing you to use the following verification environments: - Simulink cooperative verification by placing HDL blocks on Simulink diagrams - MATLAB direct interface using MATLAB files (.m files) from HDL test benches In this webinar, we will explain how to use the MATLAB/Simulink cooperative verification interface and the flow from simulation to result verification.