Free Webinar: Simplifying DO-254 Compliance in FPGA Design

Equipped with features suitable for FPGA design and verification.

Active-HDL is an integrated solution for FPGA design creation and simulation in a team environment that operates on Windows. The Active-HDL integrated design environment (IDE) includes complete HDL and graphical design tools, as well as a mixed-language simulator for RTL/gate-level, enabling the development and verification of FPGA designs in a short period of time. *For more details, please download the PDF (English version) or feel free to contact us.*

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We will meet the verification needs of engineers creating next-generation FPGAs and SoCs!

Riviera-PRO meets the verification needs of engineers creating next-generation cutting-edge FPGAs and SoCs. It enables the maximization of test bench productivity, reusability, automation through the integration of high-performance simulation engines and debugging features at various levels of abstraction, as well as support for the latest languages and verification library standards. *For more details, please refer to the PDF materials or feel free to contact us.*

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Static design analysis tool that works on Windows/Linux.

"ALINT-PRO" is a verification solution that analyzes RTL code written in VHDL, Verilog, and SystemVerilog, focusing on coding styles and naming conventions, mismatches between RTL and synthesis results, smooth and optimal synthesis, correct FSM descriptions, issues in the later stages of design, problems with clock and reset trees, CDC, RDC, DFT, and coding for portability and reuse. This solution performs static analysis based on RTL and SDC (Synopsys Design Constraints) source files, identifying critical design issues early in the design phase and significantly contributing to the reduction of design time. By running ALINT-PRO before RTL simulation and logic synthesis, you can prevent design issues from propagating to downstream processes in the design flow, thereby reducing the number of revisions needed before design completion. *For more details, please refer to the PDF materials or feel free to contact us.*

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We would like to express our congratulations on the continued prosperity of your esteemed company. Our company will be exhibiting at the following trade show, where we will introduce a number of products, including new ones. We sincerely apologize for the inconvenience during your busy schedule, but we would like to invite you to attend this event. 【 Exhibition Name 】 31st Measurement and Measurement Exhibition INTERMEASURE 2024 Official Website: https://intermeasure.org/itms2024/ 【 Dates 】 From __ (Wednesday) to __ (Friday), 202_ 【 Venue 】 Tokyo Big Sight (Tokyo International Conference Center) East Hall (Booth Number: ___) 【 Exhibited Products 】 - Air Leak Tester - Hydrogen Leak Detector - Pin Hole (Reference Test Piece) and more. For more details, please refer to the "Related Materials" (PDF file) below.

In connectors that connect various hardware such as automobiles, industrial equipment, and communication devices, low-cost Sn-plated products are widely used. However, there are also cases where attention is needed regarding the reliability specific to Sn-plated contacts. In this webinar, based on actual connector failure cases that have occurred in the market, we will explain the process leading to the identification of causes for typical failure modes such as: - Whiskers (short circuit failures) - Fretting wear (contact failures) Furthermore, we will systematically introduce the organization of failures through the FTA (Fault Tree Analysis) of the entire connector, as well as each failure mechanism. ■ Technical content to be explained: - FTA structure of connector failures - Mechanism of whisker formation and evaluation methods - Mechanism of fretting wear and evaluation methods ■ Introduction of future evaluation technologies: - High-temperature and high-humidity fretting wear testing (scheduled for introduction in December 2026)

Understanding TLM Overview It has become increasingly clear that traditional RTL modeling techniques alone are insufficient for the design and verification of large-scale ASICs/SoCs and FPGAs. As a result, the concept of Transaction Level Modeling (TLM) has been widely adopted, and it has become essential in verification methodologies such as UVM. In this webinar, we will introduce TLM using terminology explanations and implementation examples with simple sample designs.

DO-254 specifies a rigorous and requirements-based process for FPGA design development that emphasizes safety, reliability, and compliance with regulations. This process includes key steps such as defining verifiable requirements, developing design elements with ensured traceability, creating high-quality RTL code, and conducting comprehensive verification. Each phase is essential for preventing hardware failures and achieving robust designs. In this webinar, we will introduce the processes necessary to achieve compliance with DO-254 in aircraft-mounted FPGA design. Additionally, we will also present tools and methods for optimizing the design and verification workflow.

＼Utilizing HPLC Analysis and Separation for More Efficient Synthetic Research／ We will hold a webinar where you can attend the content that was well-received at the seminar held in July. ▶Reduction of analysis time ▶Efficiency in impurity analysis ▶Expansion of HPLC/LC-MS utilization ▶Introduction of automation and the latest workflows In a special lecture, Dr. Kanako Kumada from the Catalysis Chemistry Research Division of the National Institute of Advanced Industrial Science and Technology will present on "Autonomization of Organic Synthesis Experiments - Aiming for Transformation of Research Processes." 【Event Overview】 ▶Date: Thursday, August 20, 2026 ▶Time: 15:00 - 16:45 (Streaming starts at 14:45) ▶Venue: Online ▶Participation Fee: Free We look forward to the participation of everyone considering improvements in analytical efficiency in synthetic research and the expansion of HPLC and LC/MS utilization.