RTL Code Analysis and Verification Solution ALINT-PRO

DO-254 specifies a rigorous and requirements-based process for FPGA design development that emphasizes safety, reliability, and compliance with regulations. This process includes key steps such as defining verifiable requirements, developing design elements with ensured traceability, creating high-quality RTL code, and conducting comprehensive verification. Each phase is essential for preventing hardware failures and achieving robust designs. In this webinar, we will introduce the processes necessary to achieve compliance with DO-254 in aircraft-mounted FPGA design. Additionally, we will also present tools and methods for optimizing the design and verification workflow.

The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standards, how they are implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. This webinar will demonstrate the benefits of using ALINT-PRO to enforce coding standards and streamline the overall design review to meet the objectives of DO-254.

This webinar is aimed at those interested in CDC (Clock Domain Crossing) verification in FPGA design, and will cover the following topics: * What are CDC issues? * General approaches and precautions * Considerations for synchronizers in FPGA design * Solutions for CDC verification Additionally, for those interested, we will provide a one-month evaluation license for ALINT-PRO, a CDC/RDC verification solution offered by Aldec. We will also assist with the execution of the verification. If you have struggled with CDC issues in the past or are looking to start CDC verification, please join us.

Recent hardware design has seen an increase in scale and complexity, which may lead to prolonged design verification processes. In this context, there is growing attention on cleaning up design code before design verification. Cleanup can be performed relatively quickly and significantly reduces the time and effort required for design verification. Additionally, as SystemVerilog (design) becomes more prevalent in hardware design, the importance of checking design code using these tools is also increasing. ALINT-PRO can statically verify most common SystemVerilog (design) elements, allowing for the early detection of critical design issues in the design cycle. In this webinar, we will introduce the issues related to SystemVerilog and the rules for checking them.