Yonata Electronics Product Lineup

The B3224 is a high-performance Bit Error Rate Tester (BERT) for physical layer characteristic evaluation and consistency testing. With excellent signal quality, a wealth of features, and flexible testing modes (integrated MCB or remote head), it provides powerful performance and flexibility from research and development to manufacturing testing of high-speed serial circuit products. It supports data rates from 24.33 to 120 Gbaud. The test patterns include various PRBS, SSPRQ, JP03A/B, Square Wave, and custom-defined patterns. 【Key Specifications (Partial)】 ■ Output Signal: Differential PAM4/NRZ (AC Coupled) ■ Output Amplitude: 800 mVp-p (Differential) ■ Rise/Fall Time: < 4.5 ps ■ Input Signal: Differential PAM4/NRZ (AC Coupled) ■ Clock Mode: Built-in Clock Recovery *For more details, please download the PDF or feel free to contact us.

The "SWT5100" is a high-performance wafer-level test system designed for automated testing of silicon photonics wafers. It offers a fully automated testing process from wafer loading to optical alignment. Equipped with a chuck capable of temperature control from 25°C to 150°C, it supports optical, DC, and RF testing. It accommodates both GC and EC coupling and can be flexibly configured from single fibers to fiber arrays. 【Main Specifications (Partial)】 ■ Supported Wafer Size: 8 to 12 inches ■ Supported Wafer Thickness: 200 to 2000 um ■ Chuck Temperature Range: 25°C to 150°C ■ Supported Tests: Optical, DC, RF ■ Coupling Method: Grating coupling and edge coupling *For more details, please download the PDF or feel free to contact us.

The "PPT8200" is a high-performance parallel parametric test system designed with a "Per-Pin" architecture to optimize test efficiency. Equipped with SMUs and PGUs for each pin, it achieves over 50% higher throughput compared to traditional serial testers. The advanced software environment simplifies the development of test programs. It accelerates mass production launches, supports array testing, and provides a solution that balances high reliability and cost efficiency. 【Key Specifications (Partial)】 ■ Architecture: Per-Pin Architecture ■ Number of Pins: 48 Pins ■ Configuration: Per-Pin SMU, Per-Pin PGU ■ Voltage Range: ±200V ■ Current Range: ±1A ■ Throughput: >50% improvement compared to serial testers *For more details, please download the PDF or feel free to contact us.