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Verilog-HDL JPEG compression IP core Compression method: JPEG Base Line method Input format: RGB 8:8:8 Output format: YUV 4:2:0 4:2:2 4:4:4 Huffman coding: Standard settings (Annex K) used Can also be set in registers Quantization table: Standard settings (Annex K) used Can also be set in registers

• Other semiconductors

JPEG Decode Verilog-HDL IP Core YUV Formats: 4:2:0 4:2:2 4:4:4 Processing Markers: SOI, APP, DQT, DHT, SOF0, SOS, EOI All others will be ignored Output Format: RGB 8:8:8 Huffman Codes: Generated from header information Quantization Table: Generated from header information

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This process overlays character images (sprites) onto a background image. The maximum image size is 1024x1024. Arbitrary angle rotation in 0.35-degree increments. During rotation, a bi-linear interpolated image is created. Mirror flipping. Alpha blending. The maximum number of overlays is 16.

• Other semiconductors

P1_Scale performs image scaling using multi-rate signal processing in hardware. The maximum image size is 1024x1024, and the scaling ratio is N/M where N and M can be 1, 2, 3, 4, 5, 6, 7, or 8.

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