We will exhibit at the 1st [Kyushu] Semiconductor Industry Exhibition.

Newly developed copper sulfate plating chemicals for wiring of semiconductor wafers.

As the functionality, performance, and miniaturization of semiconductors continue to evolve, new technologies related to three-dimensional integration of semiconductors are being developed one after another. Consequently, addressing the miniaturization of wiring (narrow pitch) and heat dissipation measures has become increasingly important. To meet various demands, our company has newly developed sulfuric acid copper plating chemicals, the TORYZA LCN series, for semiconductor wafer wiring.

• Chemicals

TORYZA LCN SP, the optimal electroplating solution for forming copper pillars on semiconductor wafers and package substrates.

Solder balls have been widely used in semiconductor packaging. However, due to the increase in pin count (the number of terminals on the substrate), the increase in the number of chips being packaged, and the reduction in bonding area, solder bumps with a diameter of about 100µm are becoming insufficient for high-density packaging. As an alternative, attention is being drawn to a method that involves forming a redistribution layer (RDL) on the semiconductor and using copper pillars for bonding. Our company has developed the optimal additive for copper pillars, TORYZA LCN SP. TORYZA LCN SP can also be used to form ultra-fine electrodes on the build-up layer of the package substrate.

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Supports high aspect ratio filling, copper sulfate plating additive for silicon interposers - TORYZA LCN SV.

With the advancement of semiconductor performance and functionality, packaging technologies related to chiplets that implement multiple chips with different functions on a single substrate and three-dimensional integration are gaining attention. Among these, silicon interposers with wiring formed on silicon are attracting interest because they can miniaturize the length and width of the wiring, thereby enhancing the transmission capability of high-frequency signals. Our company has developed TORYZA LCN SV as an additive for silicon interposers that supports high aspect ratio filling. TORYZA LCN SV excels in embedability into TSVs, achieving void-free and low film thickness high aspect ratio filling.

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Copper sulfate plating additive for semiconductor wafers, high heat dissipation and high current applications - TORYZA LCN SD.

Smartphones are widely used not only for calls but also for content viewing such as music and videos, online shopping, and in industries like automobiles, smart home appliances, and robotics. Mobile communication devices like cell phones and tablets have undergone significant evolution approximately every 10 years, with their maximum communication speeds increasing by about 1,000,000 times over the past 30 years. Additionally, semiconductors used in servers and high-performance computers are required to achieve even higher performance and multifunctionality. Our company has recently developed a new copper sulfate plating additive, TORYZA LCN SD, which is optimal for low aspect ratio via filling. TORYZA LCN SD can be widely applied to microbumps that join semiconductor chips and build-up wiring boards, as well as thermal vias used for heat dissipation in trench wiring on wafers and power semiconductors.

• Chemicals

FOWLP, FOPLP, and next-generation semiconductor package substrates, as well as ultra-fine wiring copper sulfate plating additives - TORYZA LCN FRV.

In recent years, semiconductor packaging technology has gained attention with FOWLP and FOPLP, which allow for an increase in the number of terminals relative to chip area by forming a redistribution layer on the wafer and expanding the terminals to the outside of the chip (Fan Out), in contrast to the conventional FC-BGA that is disadvantageous for thinness and cost reduction. Our company has developed a new copper sulfate plating additive for the formation of the redistribution layer in FOWLP and FOPLP. This product excels in film thickness uniformity and rectangularity of pattern shape, and it also accommodates filling of small-diameter vias. Additionally, to support the increase in the number of terminals on the chip side, the formation of ultra-fine wiring layers on the build-up layer of conventional FC-BGA is also being considered. This product is optimal for the formation of ultra-fine wiring in next-generation semiconductor package substrates.

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Plating chemicals, total proposals for surface treatment processes and equipment, aluminum electrodes on wafers, UBM formation, plating process.

UBM (Under Barrier Metal) employs processes such as electroless Ni/Au plating and electroless Ni/Pd/Au plating. However, conventional processes have faced challenges such as localized corrosion of aluminum electrodes, poor appearance of plating, and poor adhesion. Additionally, in recent years, as power semiconductors have progressed towards higher voltage and higher current, there has been a demand for further heat resistance in electroless plating films. In response, we have developed a new UBM formation plating process called "TORYZA EL PROCESS," which suppresses film reduction and localized corrosion of aluminum electrodes while providing excellent uniform deposition, smoothness, and adhesion of electroless Ni plating. Along with the electroless plating equipment for UBM formation, "TORYZA EL SYSTEM," we offer a comprehensive proposal for plating chemicals, surface treatment processes, and equipment for semiconductor back-end processes.

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Plating chemicals, total proposals for surface treatment processes and equipment, electroless plating equipment for UBM formation for wafers.

Leveraging the know-how acquired as a surface treatment and plating chemicals manufacturer, we designed and developed the electroless plating system "TORYZA EL SYSTEM" for UBM formation in collaboration with equipment manufacturers. Along with the plating process "TORYZA EL PROCESS" for UBM formation on aluminum electrodes on wafers, we offer a comprehensive proposal for plating chemicals, surface treatment processes, and equipment for semiconductor back-end processes.

• Chemicals

Achieving thin film deposition of non-electrolytic copper plating! It greatly contributes to the formation of fine circuits on semiconductor package substrates and the improvement of via connection reliability!

In recent years, with the miniaturization and high performance of electronic devices, semiconductor devices have also become more refined and functional. There is a growing demand for further miniaturization of wiring and reduction of via diameters in semiconductor package substrates that connect semiconductor devices to the main substrate. Okuno Pharmaceutical Industry has newly developed products to meet the demands for fine wiring. Highest via connection reliability: Electroless copper plating solution: OPC FLET Copper - Achieves crystal continuity at the bottom of the via - Conventional baths see a significant increase in resistance due to a decrease in the thickness of the electroless copper plating film OPC FLET Copper shows good conductivity even at low film thickness - Controls the plating deposition rate - The deposition rate becomes gradual over time, suppressing deposition on copper - Conventional baths tend to have excessive surface film thickness OPC FLET Copper achieves sufficient coverage at low film thickness - Excellent connection reliability for small-diameter vias

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Features ● Equipped with Intel Core Ultra 5 125H ● Dual Channel DDR5 5600MHz × 2 slots (up to 96GB) (sold separately) ● HDMI 2.0 × 4 ● M.2 3042/3052 B-Key × 1, 2230 E-Key × 1, 2280 M-Key × 1 (PCIe Gen4 [x4], NVMe) (sold separately) ● USB 2.0 × 5, USB 3.2 × 3, USB 3.2 Gen 1 (Type-C) × 1 ● LAN × 2 ● 12V DC input power ● OOB (Out-of-Band Management) module compatible: MOD-RMB (via i210-AT) * This model does not include memory, storage, or OS.

Features ● Compatible with Intel Core Ultra 200S series ● DDR5 SODIMM x 2 (up to 96GB) ● PCIe x4 x 1, M.2 3042/52 B-key x 1 ● USB2.0 x 4, USB3.2 Gen2 x 2 (rear I/O), USB3.2 Gen1 x 1, USB2.0 x 1 (pin header) ● SATA 6Gb/s x 2 ● HDMI 2.0 x 2, DP 1.4 x 1 ● DC input 19V ~ 24V * This model does not include memory, storage, or OS.

Features ● Equipped with Intel Processor N97 ● DDR5 SODIMM up to 16GB (sold separately) ● M.2 2280 M-Key x 1 (Auto Detect, PCIe [x1] & SATA Mode), M.2 2230 E-Key x 1, M.2 3042/52 B-Key x 1 ● USB3.2 x 1 (rear I/O), USB2.0 x 4 (pin header) ● PoE x 1, GbE LAN x 1 ● 12V DC input ● OOB onboard * This model does not include memory, storage, or OS.

● This is a leak testing device for small electronic components that does not use fluorinated inert liquids (PFAS-free). ● There is no longer a need for unstable visual confirmation through liquid immersion testing. It adopts a quantitative testing method that allows for stable pressure leak testing. ● It is a tabletop leak testing device specifically for gross leaks, with accuracy equal to or greater than that of liquid immersion testing. ● The detectable range is approximately 1×10⁻² Pa·m³/s to 1×10⁻⁶ Pa·m³/s (varies depending on the target product). ● It is suitable for sealed structures ranging from a few millimeters to a maximum of 80 × 70 mm. Please feel free to contact us for more information!

The "Mechanical Stitch Method" by Nichinichisui Road Machinery Co., Ltd. is a new technique that allows for the repair of metal cracks without the application of heat. By using special bolts and reinforcement plates, cracks are physically removed, and repairs are made without causing any thermal impact to the base material. Repairs can be carried out in environments where open flames cannot be used. Since no heat is applied, the disassembly of equipment is minimized. ◎ For more details, please contact us. ◎ If a detailed technical explanation is needed, please contact us.