ECC with BCH Algorithm IP Core
Configurable encoding/decoding block! Parallelized BCH encoder/decoder.
The "ECC with BCH Algorithm IP Core" is an IP core designed to add error detection/correction functionality using industry-standard BCH class error correction codes, preventing data loss or corruption over noisy and unreliable communication channels. If the BCH configuration is not covered, it can be customized to support a wide range of BCH codes. It can be used in a variety of applications, including data storage devices (SATA, SAS, FLASH), two-dimensional barcodes, satellite communication/telemetry, radio signal recording, wireless communication, high-speed modems such as ADSL and xDSL, and power line standards. 【Specifications】 ■ High bandwidth and low latency through parallel processing ■ Configurable encoding/decoding block structure ■ Configurable word length/block size ■ FIFO data interface of 32, 64, 128, or 256 ■ Parallelized BCH encoder/decoder *For more details, please download the PDF or feel free to contact us.
- 企業：富士ソフト インダストリービジネス事業部
- 価格：Other
