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core Product List and Ranking from 30 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

core Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

  1. 昭和丸筒 Osaka//Paper and pulp
  2. 日本継手 Tokyo//Manufacturing and processing contract 東京営業部
  3. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  4. 4 DIAMET CORPORATION Niigata//Machine elements and parts
  5. 4 山本精機 Nagano//Manufacturing and processing contract 本社、THAI工場
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core Product ranking

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

  1. Dual-structure core for reducing roll tendency and shaft diameter conversion (Lotus Core) 昭和丸筒
  2. Core joint C core / CD core 日本継手 東京営業部
  3. Motor core by vacuum impregnation and lamination. 山本精機 本社、THAI工場
  4. 4 Nessum (formerly HD-PLC) IP core Panasonic Holdings Corporation / Nessum Department
  5. 5 Soft magnetic material laminated motor core

core Product List

196～210 item / All 245 items

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IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N13"

IP core "AndesCore N13"

With an 8-stage pipeline and a clock frequency exceeding 1GHz, the core delivers excellent performance of 2.05 DMIPS/MHz!

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N10"

IP core "AndesCore N10"

You can bridge the internet connection of ZigBee, Bluetooth, or WiFi sensor devices!

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore E8"

IP core "AndesCore E8"

FlashFetch improves performance while saving power!

The "AndesCore E8" is a power-efficient and compact embedded controller enabled by the unique Andes Custom Extension (ACE). With its proprietary ACE environment, designers can specify architectural elements suitable for IoT applications. Using Andes' Custom-Optimized Instruction Development Tools (COPILOT), designers can create custom instructions that differentiate their products and designs from competing products based on standard instruction set processors. 【Specifications】 ■ Class-leading performance per MHz ■ Andes Custom Extension (ACE) significantly improves performance efficiency ■ Small footprint with fewer gates and high code density ■ Faster flash access and reduced power consumption through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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SATA Device ADCI IP Core for FPGA and ASIC

SATA Device ADCI IP Core for FPGA and ASIC

Supports power modes (partial/slumber)! The DATA interface uses FIFO.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SATA RAID IP Core for FPGA and ASIC

SATA RAID IP Core for FPGA and ASIC

Fully compliant with SATA industry specifications! Operates with drives that are multiples of 2.

The "IP Core for SATA RAID for FPGA/ASIC" provides RAID 0 (striping and concatenation) and splits data across multiple storage endpoints to achieve higher system storage performance. It is designed to operate with extremely low latency during data transfers between SATA storage devices and backend data interfaces. This can be used for RAID 0 storage solutions that require high speed and large capacity. 【Specifications (excerpt)】 - Supports RAID 0 (striping and concatenation) - Operates with an even number of drives - SATA transfer rates: 1.5Gbps, 3.0Gbps, and 6.0Gbps (supports automatic speed negotiation) *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SAS Target IP Core for FPGA and ASIC

SAS Target IP Core for FPGA and ASIC

Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps! Equipped with automatic credit control function.

The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe Host Accelerator IP Core

NVMe Host Accelerator IP Core

It is an application layer equipped with an interface to the processor!

We would like to introduce the "NVMe Host Accelerator IP Core" that we handle. This product is an NVMe host IP core from IntelliProp that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) with 8 lanes. It also features queuing and issuing capabilities for NVMe commands, allowing you to use it as a solution for high-speed data access to NVMe target devices. 【Specifications (excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Supports automatic initialization using PCIe hard blocks ■ Compatible with third-party PCIe Root Complex IP cores ■ Number of queues is adjustable (up to 64K) ■ Maximum data buffer size of 1GB *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe-to-NVMe Bridge

NVMe-to-NVMe Bridge

Supports automatic initialization using PCIe hard blocks!

The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.

  • ASIC

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AES-GCM Encryption IP Core

AES-GCM Encryption IP Core

Multiple independent data streams! You can choose the AES encryption key from 128 or 256 bits.

We would like to introduce the 'AES-GCM Encryption IP Core' that we handle. This is an AES-GCM (Galois Counter Mode) encryption IP core that enables users to perform encryption/decryption and authentication of packets or data streams. It supports AES-GCM encryption levels of 128 or 256 bits and is capable of data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. 【Specifications】 ■ AES encryption key selectable from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput *For more details, please download the PDF or feel free to contact us.

  • ASIC

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[YUSEUNG] Inductor Core

[YUSEUNG] Inductor Core

Inductor core

Inductor Core - A manufacturing business that develops various components using soft magnetic powder materials. - Plans to advance the development of high-value-added businesses such as magnetic sheets (nano-crystal ribbons) and functional components (paste, amorphous/nanocrystalline). Technology - Dry coating insulation ensures that each powder particle is uniformly coated. - This dry technology is advantageous not only in terms of process time and costs compared to wet processes but is also applicable as an environmentally friendly method.

  • Inductor Coil

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