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core Product List and Ranking from 30 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

core Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

  1. 昭和丸筒 Osaka//Paper and pulp
  2. 日本継手 Tokyo//Manufacturing and processing contract 東京営業部
  3. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  4. 4 DIAMET CORPORATION Niigata//Machine elements and parts
  5. 4 山本精機 Nagano//Manufacturing and processing contract 本社、THAI工場
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core Product ranking

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

  1. Dual-structure core for reducing roll tendency and shaft diameter conversion (Lotus Core) 昭和丸筒
  2. Core joint C core / CD core 日本継手 東京営業部
  3. Motor core by vacuum impregnation and lamination. 山本精機 本社、THAI工場
  4. 4 Nessum (formerly HD-PLC) IP core Panasonic Holdings Corporation / Nessum Department
  5. 5 Soft magnetic material laminated motor core

core Product List

226～240 item / All 245 items

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IP core "AndesCore D10"

IP core "AndesCore D10"

The optimized DSP library and C/C++ compiler make programming algorithms easier!

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N8"

IP core "AndesCore N8"

Reduce memory usage and lower customers' silicon costs!

The "AndesCore N8" is an IP core that provides a long-term roadmap for customers requiring an upgrade path from 8-bit cores. With the ability to process both 16-bit and 32-bit instructions, it enables a reduction in the ROM size of program data. While being a computing platform comparable to an 8-bit controller, it achieves the performance of an advanced 32-bit processor. 【Specifications】 ■ Excellent overall performance ■ Vector interrupts for low-latency interrupt handling ■ Small footprint with fewer gates and high code density ■ Faster Flash access and power reduction through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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SATA Host APP for FPGA and ASIC IP Cores

SATA Host APP for FPGA and ASIC IP Cores

Equipped with a self-test! Supports power modes (partial/slumber).

We would like to introduce our "SATA Host APP IP Core for FPGA and ASIC." This is an IP core for SATA hosts that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It consists of the PHY layer, LNK layer, TRN (Transport) layer, application layer, SerDes, and FIFO interface. 【Specifications】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Uses FIFO for the DATA interface ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SATA Host AHCI IP Core for FPGA/ASIC

SATA Host AHCI IP Core for FPGA/ASIC

It can widely support systems that require a SATA host!

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SAS Initiator IP Core for FPGA/ASIC

SAS Initiator IP Core for FPGA/ASIC

OOB sequence and speed negotiation sequence support!

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC

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IP core for FPGA/ASIC NVMe Target

IP core for FPGA/ASIC NVMe Target

Register access from the processor is available! Command interrupt support is included.

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe-to-SATA Bridge

NVMe-to-SATA Bridge

Available for LBA remapping, data encryption, data compression, and endpoint aggregation!

We would like to introduce the 'NVMe-to-SATA Bridge' handled by Fujisoft Inc. This product is an IP core for creating an NVMe-to-SATA protocol bridge using NVMe Host IP core and SATA AHCI Host IP core. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. 【Specifications (Excerpt)】 ■ NVMe protocol interface complies with NVMe 1.4 standard ■ SATA interface complies with SATA 3.3 specification ■ Supports industry-standard AHCI (Advanced Host Controller Interface) v.1.3.1 ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks *For more details, please download the PDF or feel free to contact us.

  • ASIC

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ECC with BCH Algorithm IP Core

ECC with BCH Algorithm IP Core

Configurable encoding/decoding block! Parallelized BCH encoder/decoder.

The "ECC with BCH Algorithm IP Core" is an IP core designed to add error detection/correction functionality using industry-standard BCH class error correction codes, preventing data loss or corruption over noisy and unreliable communication channels. If the BCH configuration is not covered, it can be customized to support a wide range of BCH codes. It can be used in a variety of applications, including data storage devices (SATA, SAS, FLASH), two-dimensional barcodes, satellite communication/telemetry, radio signal recording, wireless communication, high-speed modems such as ADSL and xDSL, and power line standards. 【Specifications】 ■ High bandwidth and low latency through parallel processing ■ Configurable encoding/decoding block structure ■ Configurable word length/block size ■ FIFO data interface of 32, 64, 128, or 256 ■ Parallelized BCH encoder/decoder *For more details, please download the PDF or feel free to contact us.

  • ASIC

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AES-XTS Encryption IP Core

AES-XTS Encryption IP Core

You can choose the AES encryption key from 128 or 256 bits! The encryption algorithm complies with FIPS-197.

We would like to introduce the 'AES-XTS Encryption IP Core' that we handle. This product is an AES-XTS encryption IP core that enables full disk encryption for storage devices. It supports AES-XTS encryption levels of 128-bit or 256-bit and allows encryption tailored to data transfer rates of SATA 6Gbps, SAS 12Gbps, and PCIe (NVMe) Gen4 x4 lanes. 【Specifications】 ■ FIPS-197 compliant AES-XTS algorithm ■ AES encryption key selectable from 128 or 256 bits ■ Configurable number of encoding/decoding pipelines ■ Independent management of encryption/decryption keys ■ Simultaneous support for encoding and decoding ■ Supports integer multiples of 16-byte data unit sizes *For more details, please download the PDF or feel free to contact us.

  • ASIC

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AES-CTR Encryption IP Core

AES-CTR Encryption IP Core

Compatible with OpenSSL's AES-256-CTR encryption mode! Multiple independent data streams.

The "AES-CTR Encryption IP Core" is an IP core for AES-CTR (Counter Mode) encryption that allows users to perform encryption/decryption of packets or data streams. It supports AES-CTR encryption levels of 128 or 256 bits and enables data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. Additionally, it is compatible with OpenSSL's AES-256-CTR encryption mode. 【Specifications】 ■ AES encryption key can be selected from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput ■ Compatible with OpenSSL's AES-256-CTR encryption mode *For more details, please download the PDF or feel free to contact us.

  • ASIC

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Exhibit: Motor Core

Exhibit: Motor Core

The material used is electromagnetic steel sheet SPCC! This is a display item processed by laminated pressing.

We would like to introduce our exhibition item, the "Motor Core," which has been processed by our company. The material used is electrical steel sheet/SPCC, with a thickness ranging from t0.3 to 1.0. The processing method involved laminated pressing. Please feel free to contact us if you have any inquiries. 【Exhibition Item Overview】 ■ Material: Electrical steel sheet/SPCC ■ Thickness: t0.3 to 1.0 ■ Processing Method: Laminated pressing *For more details, please refer to the PDF document or feel free to contact us.

  • Processing Contract

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Ball bearing structure of the slide core in injection molding molds.

Ball bearing structure of the slide core in injection molding molds.

Proposal for Injection Molding Mold Slide Core Structure

【Aim of Improvement】 1. Reduction of friction resistance (coefficient) - from friction to rolling 2. Increase in slide angle due to reduced friction resistance ⇒ reduction in die height 3. Improvement in durability and maintainability due to reduced friction resistance and so on PAT.PENDING

  • Plastic Mould
  • Rubber mold
  • Resin mold

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Recycled powder cores that contribute to carbon neutrality.

Recycled powder cores that contribute to carbon neutrality.

Not only will we reduce CO₂, but we will also contribute to the realization of a circular economy.

A recycling example of powdering used powder cores and reforming them into powder cores again. - Since powder cores are easy to crush, the cores are crushed, processed, and reused. - This contributes not only to CO₂ reduction but also to the realization of a circular economy.

  • Other motors

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