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core Product List

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IEEE1588-2008 PTP Time Synchronization IP Core

IEEE1588-2008 PTP Time Synchronization IP Core

Providing IEEE1588-2008 PTP time synchronization solutions as an IP core. Synchronizing devices on Ethernet (LAN) with nanosecond precision.

Oregano Systems offers timing synchronization solutions compliant with IEEE1588-2008 Precision Time Protocol as IP CORE. It provides syn1588 Clock_S for serial connection to external CPUs and syn1588 Clock_M for parallel connection, available in netlist or source code. Synchronization in the nanosecond range over Ethernet is possible. Support for 802.1AS will be available starting summer 2016.

  • syn1588 Clock_M GMII.jpg
  • LAN construction and wiring work

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PTP software for RX family 'pwDadBerry-FRX'

PTP software for RX family 'pwDadBerry-FRX'

We will implement it on Renesas Electronics' RX microcontrollers to build various sensor networks.

The RX64M (manufactured by Renesas Electronics), equipped with IEEE1588 functionality, is a device that easily enables daisy chain wiring. By implementing our PTP software on the RX64M, which has two Ethernet ports, it can also function as a BC (Boundary Clock). Synchronization signals of 51.2KHz, 102.4KHz, 204.8KHz, 409.6KHz, and 819.2KHz, necessary for sensor control, are generated using a PLD. Please realize the construction of various sensor networks that leverage the features of the RX microcontroller capable of daisy chain configuration through the implementation of PTP software for the RX family.

  • Other embedded systems (software and hardware)

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IP core "AndesCore N22"

IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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