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core(motor) - List of Manufacturers, Suppliers, Companies and Products

core Product List

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OTP Non-volatile Memory IP Core 'PermSRAM'

OTP Non-volatile Memory IP Core 'PermSRAM'

Achieving affordable and reliable shipping inspections! We support high quality and stable yields.

"PermSRAM" is an OTP non-volatile memory IP core that can be manufactured using standard logic processes. It provides non-volatile memory that can be written only once for a wide range of processes, from the 0.18um generation to advanced 28nm generations and beyond. Customization is possible for various non-volatile memory core applications, ranging from 64b latch types to 1MByte code storage memory. 【Features】 ■ World-class smallest area ■ Reverse engineering resistance ■ Low voltage writing ■ Equipped with test circuits ■ Automotive grade (guaranteed up to 150℃) *For more details, please refer to the PDF document or feel free to contact us.

  • Memory
  • Other electronic parts

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IP core "AndesCore E8"

IP core "AndesCore E8"

FlashFetch improves performance while saving power!

The "AndesCore E8" is a power-efficient and compact embedded controller enabled by the unique Andes Custom Extension (ACE). With its proprietary ACE environment, designers can specify architectural elements suitable for IoT applications. Using Andes' Custom-Optimized Instruction Development Tools (COPILOT), designers can create custom instructions that differentiate their products and designs from competing products based on standard instruction set processors. 【Specifications】 ■ Class-leading performance per MHz ■ Andes Custom Extension (ACE) significantly improves performance efficiency ■ Small footprint with fewer gates and high code density ■ Faster flash access and reduced power consumption through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D10"

IP core "AndesCore D10"

The optimized DSP library and C/C++ compiler make programming algorithms easier!

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore NX25F"

IP core "AndesCore NX25F"

Optimized for high operating frequency and high performance! Supports single-precision/double-precision floating-point instructions.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N25F"

IP core "AndesCore N25F"

High code density 16/32-bit mixed instruction format!

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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NVMe-to-NVMe Bridge

NVMe-to-NVMe Bridge

Supports automatic initialization using PCIe hard blocks!

The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.

  • ASIC

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