富士ソフト List of Products and Services

Rambus's "Quantum Safe Core Library" is a product that provides cryptographic algorithms for the post-quantum cryptography (PQC) era, focusing on minimizing resource usage and dependencies. The Quantum Core Library is a "bare-metal" software implementation that is OS-independent and has a small footprint. Please feel free to contact us when you need assistance. 【Features (excerpt)】 ■ Fast and minimal quantum-safe software library ■ Footprint: 46KB on a 32-bit ARM platform (can be further reduced if algorithms are not needed) ■ "Bare-metal," no OS or hardware dependencies ■ Supports integration with third-party software or hardware Implementations of SHA-256, SHA-512, and SHAKE256 *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus's "SphincsLib" is a standalone "bare metal" software library that implements the SLH-DSA FIPS 205 standard. It supports integration with third-party software or hardware. During the maintenance period, we provide engineer-level support and updates. Please feel free to contact us when needed. 【Features (excerpt)】 ■ High-speed, minimal SLH-DSA software library ■ "Bare metal," no OS or HW dependency ■ A single API for both HW and SW ■ Supports integration with third-party software or hardware ■ Implementations of SHA-256, SHA-512, and SHAKE256 *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus's "SHSlib" is a standalone stateful hash-based signature software library that provides stateful hash-based signature verification. The software implements SHA-256 operations and can be integrated with Rambus EIP-120 and hardware. Furthermore, it can be accelerated through integration with another hardware SHA core. This library is optimized for minimal footprint and stack usage, designed to be independent of hardware and OS. 【Features (excerpt)】 ■ Fast and minimal LMS and XMSS software library ■ No bare metal, OS, or hardware dependencies ■ Hardware acceleration options for SHA-256 ■ A single API for both hardware and software ■ Supports integration with third-party software or hardware SHA-256 implementations *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus' "Secure Boot Solution (formerly Inside Secure)" is a product that provides tools to integrate security into the system boot sequence of embedded devices. This solution protects the boot process of SoCs and application processors using strong encryption. By encrypting images with robust encryption technology, it prevents the images from being analyzed. 【Features (excerpt)】 ■ Secure boot ROM code library for integration into bootloaders ■ Secure boot image generation tool for signing and encrypting images ■ Cryptographic algorithms ・Hash algorithms: SHA-244/SHA-256 ・Asymmetric cryptographic algorithms: ECDSA (P224 and P256) ・Symmetric cryptographic algorithms: AES (128-256) *For more details, please refer to the related links or feel free to contact us.

• Other Software

We would like to introduce our "Quantum Safe Crypto Library." It includes all classical cryptographic algorithms such as encryption algorithms, MAC algorithms, and asymmetric cryptographic algorithms. This library is compatible with bare metal and various operating systems. Please feel free to contact us when you need assistance. 【Quantum Resistant Algorithms and Schemes】 ■ ML-KEM (CRYSTALS-Kyber): Key Encapsulation Mechanism ■ ML-DSA (CRYSTALS-Dilithium): Digital Signature Scheme ■ LMS: State-Holding Hash-Based Signature Scheme ■ XMSS: State-Holding Hash-Based Signature Scheme *For more details, please refer to the related links or feel free to contact us.

• Other Software

"Crypto Engine and Crypto Provider" are high-speed and flexible implementations of the OpenSSL Engine and Provider API. By using these in combination with the SafeZone FIPS Crypto Library, it is possible to provide a FIPS certified backend for OpenSSL. The separation of the provider/engine and the cryptographic module ensures maximum flexibility even when updates or modifications are necessary. 【Specifications (excerpt)】 ■ Cryptographic algorithms: AES (ECB, CBC, CFB, GCM, CCM, CTR, OFB, KW, KWP, WRAP, WRAP-PAD), 3DES, ChaCha20-Poly1305, RSA ■ Hash algorithms: SHA-1, SHA-2, SHA-3 ■ MAC algorithms: HMAC-SHA, GMAC-AES, AES CMAC ■ Digital signatures: RSA, DSA, ECDSA *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus's FIPS cryptographic library (SafeZone cryptographic library) is a cutting-edge cryptographic library that provides advanced implementations of all major cryptographic algorithms and primitives. It includes FIPS-certified cryptographic modules, standard cryptographic libraries for non-FIPS algorithms, and user-friendly cryptographic APIs for integration. This library is integrated into the IPsec toolkit and has been deployed in over 100 million devices. 【Specifications (excerpt)】 ■ Cryptographic algorithms: AES, AES-CCM, AES-GCM, AES-GCM-64, GMAC-AES, 3DES ■ MAC algorithms: SHA-1, SHA-2, GMAC-AES, AES-XCBC ■ Asymmetric cryptographic algorithms: RSA, Diffie-Hellman, ECC DH, ECC DSA, PKCS#1, PKCS#5, PKCS#7, PKCS#8, PKCS#10, PKCS#12 *For more details, please refer to the related links or feel free to contact us.

• Other Software

We would like to introduce the "Classic IPsec Toolkit" that we handle. This is a complete and highly scalable IPsec implementation that supports all relevant RFCs and standards (over 90) when servers and clients need to communicate with various types of client/server devices and interoperate with existing gateways. The Linux data plane is supported without kernel dependencies, making it suitable for deployment in high-traffic gateways and virtual environments. 【Features】 ■ High session setup rate ■ High availability (HA) ■ Easy debugging ■ Multi-tenant *For more details, please refer to the related links or feel free to contact us.

• Other Software

The "Quantum Safe IPsec Toolkit (QuickSec Quantum)" is a complete IPsec software implementation that supports Quantum Safe encryption. Quantum Safe encryption is designed to withstand attacks from quantum computers and is an essential feature for cutting-edge security products. The Quantum Safe IPsec Toolkit builds on the achievements, experience, and performance of the Rambus Classic IPsec Toolkit, leading IPsec into the era of quantum safety. 【Features】 ■ High session setup speed ■ High availability (HA) ■ Easy debugging ■ Multi-tenant ■ General-purpose data plane API *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus's IoT Security Framework is a series of embedded software toolkits designed to protect cost-sensitive devices that have limited capabilities to secure internal SoCs. It offers a rich set of security protocols, including TLS and IPsec. The IoT Security Framework, designed for IoT devices and cloud-based applications, provides a common API that delivers the necessary encryption and certificate tools. 【Features】 ■ High session setup speed ■ Capable of establishing over 3,800 IPsec tunnels per second ■ Excellent scalability with multi-core architecture ■ High availability (HA) ■ Easy debugging *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus's software security toolkit and libraries provide encryption services protected from FIPS certification or side-channel attacks, in addition to various features for securing communications. The security protocol toolkit offers high interoperability and portability for use in security gateways, cloud deployments, and IoT devices. This includes a complete implementation of key exchange protocols and a data path that encompasses all necessary cryptographic libraries. 【Specifications】 ■Quantum Safe IPsec Toolkit ■Classic IPsec Toolkit ■FIPS Cryptographic Library ■Cryptographic Engine and Cryptographic Provider *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus provides software security tools and libraries, as well as an IoT security framework as secure software. It offers a cryptographic library that has obtained FIPS 140-3 certification, providing state-of-the-art implementations of all algorithms required for IPsec or TLS. Additionally, it delivers FIPS-certified encryption using the aforementioned certified libraries with a robust implementation of the OpenSSL engine and provider API. 【Secure Toolkit and Libraries】 ■ Quantum Safe IPsec Toolkit ■ Classic IPsec Toolkit ■ FIPS Cryptographic Library ■ Cryptographic Engine and Cryptographic Provider ■ Quantum Resistant Library *For more details, please refer to the related links or feel free to contact us.

• Other Software

This product is a fully programmable hardware security core compliant with FIPS 140-3, designed from the ground up to provide quantum-resistant security for data centers and other applications requiring advanced security. Device and system architects are facing increasingly diverse security threats, including the risks posed by quantum computers. The need for hardware-based Root of Trust security implementations remains constant across various applications. This product offers extensive protection against both hardware and software attacks through advanced side-channel attack countermeasures, tamper resistance technologies, and security techniques. 【Features】 ■ Supports various security certifications up to Level 3 ■ Provides a future-proof hardware security solution ■ Enables the development of secure and reliable applications ■ Allows for the configuration of independent authorities and access levels *For more details, please refer to the related links or feel free to contact us.

• Other Software

Rambus' "Quantum Safe Engine (QSE) IP" is a product that provides acceleration for post-quantum cryptography for ASIC, SoC, and FPGA devices. This product is integrated into hardware Root of Trust or embedded secure elements, combined with the PKE-IP-85 core that accelerates classical public key cryptography and the TRNG-IP-76 core that generates true random numbers. For high-security applications that require additional protection against Differential Power Analysis (DPA) attacks, a DPA-resistant version of QSE is available. 【Features】 ■ Compliant with FIPS 203 ML-KEM and FIPS 204 ML-DSA standards ■ NIST CAVP (used in FIPS 140-3 compliant products) ■ Utilizes quantum-resistant algorithms CRYSTALS-Kyber and CRYSTALS-Dilithium ■ Includes acceleration for SHA-3, SHAKE-128, and SHAKE-256 *For more details, please refer to the related links or feel free to contact us.

• Other Software

We would like to introduce the "Post-Quantum Cryptography IP Core" that we handle. Quantum computers are capable of quickly breaking current asymmetric encryption, putting important data and assets at risk. This solution provides a hardware-level security solution that protects data and hardware from quantum computer attacks by using algorithms selected by NIST and CNSA. 【Specifications (Excerpt)】 ■QSE-IP-86: Standalone engine that enables the acceleration of post-quantum cryptography ■QSE-IP-86-DPA: Standalone engine that provides acceleration of post-quantum cryptography and a DPA-resistant cryptographic accelerator ■CryptoManager RT-634: Programmable root of trust that enables the acceleration of post-quantum cryptography ■CryptoManager RT-664: Programmable root of trust equipped with acceleration of post-quantum cryptography, DPA resistance, and FIA-protected cryptographic accelerator *For more details, please refer to the related links or feel free to contact us.

• Other Software

The Agilex3 SoC FPGA System on Module is a high-performance module equipped with a dual-core Arm Cortex-A55 (up to 800MHz) and up to 135,110 logic elements, making it ideal for industrial, medical, automotive, and aerospace applications. It features 4GB LPDDR4 memory (expandable up to 8GB), 32GB eMMC (expandable up to 128GB), and transceivers supporting 12.5Gbps, and it can operate in a wide temperature range of -40°C to +85°C. With a variety of interfaces such as PCIe Gen3 and USB OTG, it strongly supports flexible designs for edge AI and control applications.

• Circuit board design and manufacturing

At Fujisoft, we offer PMO support consulting solutions to solve issues related to project management and business efficiency. — What is PMO support consulting solution? — Fujisoft engineers participate in your software development operations from the upstream, working alongside your project managers and on-site developers to distribute the workload while observing the business environment. We promote solutions to challenges such as providing recommendations for smooth project management and improving the business environment. 【Service Contents】 ■ Business Organization and Issue Discovery Support By participating as engineers in your software development operations from the upstream, we not only reduce the business burden but also uncover implicit issues that cannot be obtained through interviews with external consulting firms. ■ Process Tuning We tune the ongoing business processes without making significant changes, implementing improvements that minimize impact on operations. ■ Business Automation We standardize and systematize work procedures. We explore automation mechanisms that maximize the use of assets held by the client and implement and operate them.

• project management
• Other contract services

At Fujisoft, we conduct a wide range of development based on the technologies cultivated in the development/manufacturing of industrial equipment, communication devices, and general medical devices, from logical design using RTL languages and prototype board development to OEM production. 【Service Overview】 ■DMS A comprehensive service from design to procurement, implementation, prototyping, and mass production. ■EMS A contract manufacturing service for electronics in the manufacturing industry. *For more details about our services, please visit our website through the related links below or feel free to contact Fujisoft. 【Service Features】 - We provide DMS/EMS with a consistent process from design and manufacturing to evaluation, tailored to customer requirements. - With a wealth of development experience across multiple products, we can select components, provide technical expertise, and ensure quality according to customer demands. - Leveraging connections with numerous partner companies, we can address requests related to small-lot, diverse production and inventory management, which are challenges in manufacturing. - We manage all interactions with various companies necessary for conducting everything from design to manufacturing.

• Circuit board design and manufacturing
• EMS
• Contract manufacturing

Black Duck SCA is an OSS management and static analysis tool that supports organizations in managing the use of OSS and associated risks through high-performance composition analysis. In preparation for the full implementation of the European Cyber Resilience Act (CRA) starting December 11, 2027, Black Duck SCA can comprehensively support the management of OSS, vulnerability countermeasures, license violation checks, and encryption risks for customer organizations and services with efficient and continuous analysis capabilities. Fujisoft partners with "Black Duck" and "Macnica," specialists in tool knowledge and vulnerability-related issues, to provide reliable support for customers implementing Black Duck SCA. 【Would you like to consult with us first?】 What should you do to comply with the Cyber Resilience Act? I want to start managing OSS/SBOM but don't know how... If you have such concerns, please feel free to consult Fujisoft! ★For those who have already started considering Black Duck SCA and want to know what benefits it offers★ Download the PDF materials or feel free to contact us!

• Software (middle, driver, security, etc.)
• Other security
• Other analyses

At Fujisoft, we are engaged in application development using cross-platform technology. We respond to various requests, including not only application development but also support for transitioning from traditional development to cross-platform. 【Features】 - By using cross-platform technology, we can achieve development that balances low cost and high quality. - We provide consistent one-stop support for all processes of app development, from requirements definition to design, development, maintenance, and operation. - Fujisoft excels in embedded development, allowing us to propose solutions that combine embedded development with application development. ~What is Cross-Platform?~ It refers to development methods and technologies that enable a single application to operate on multiple platforms. Since one code can be reused across multiple platforms, it compresses the development and maintenance periods of the app, significantly reducing costs. By keeping the development team size manageable, it allows for efficient responses to a broader user base, making it an important option in recent application development.

• Embedded applications for mobile phones and PDAs
• Software (middle, driver, security, etc.)
• Other embedded systems (software and hardware)

The "SPI Master/Slave [DFSPI]" is a device that allows you to set the polarity and phase of the serial clock signal SCK. As an option, the DFSPI controller supports HyperBus specifications and xSPI (Expanded Serial Peripheral Interface - JESD251A) specifications. Additionally, using the SPI controller allows for easy communication with most commercially available SPI flash memory. 【Specifications (Excerpt)】 ■ Equipped with software-accessible control registers to execute various flash memory commands ■ Supports clock frequencies, polarity, and phase for various devices ■ Programmable baud rate generator ■ Built-in flash command decoder that supports common flash devices *For more details, please download the PDF or feel free to contact us.

• ASIC

The "Dual Channel USART Controller [D85C30]" is an IP core for dual channel USART, designed for use with 8-bit and 16-bit microprocessors. It features asynchronous format, synchronous byte-oriented protocols, and synchronous bit-oriented protocol functions such as HDLC and SDLC. Additionally, it meets a wide range of serial communication applications and supports various serial data transfer applications (communication, LAN, etc.). [Specifications (excerpt)] ■ Software compatible with Z85C30 ■ Dual channel ■ Configuration features ■ Character-oriented mode: single synchronous, bi-directional synchronous, external synchronous ■ Bit-oriented mode: SDLC / HDLC, SDLC / HDLC Loop *For more details, please download the PDF or feel free to contact us.

• ASIC

The "HDLC/SDLC Protocol Controller [DHDLC]" is a controller used for managing HDLC/SDLC transmission frames, and it can be easily connected to 8-bit, 16-bit, and 32-bit microcontrollers. With features such as bit stuffing, address recognition, and CRC calculation, it reduces the processing load on the microcontroller. Additionally, DHDLC implements FIFO buffers for both receiving and transmitting. 【Features】 ■ Separate transmit and receive interfaces ■ Individually configurable transmit and receive FIFO buffer control ■ Bit stuffing and unstuffing functions ■ Receive address identification and transmit address insertion functions ■ Support for 2-byte or 1-byte address fields *For more details, please download the PDF or feel free to contact us.

• ASIC

The "LIN Bus Controller [DLIN]" is a controller for the Local Interconnect Network (LIN). This interface is a serial communication protocol designed primarily for use in automotive applications. Additionally, compared to CAN, LIN is slower but is ideal for communication with intelligent sensors and actuators that do not require the bandwidth of CAN. [Features] ■ Compliant with LIN 1.3, LIN 2.1, and LIN 2.2 specifications ■ Automatic LIN header processing ■ Automatic resynchronization ■ Data transfer speeds from 1 Kbit/s to 20 Kbit/s ■ Master and slave operating modes *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce the 'CAN Bus Controller [DCAN-FD]' that we handle. This product is a standalone controller for the Controller Area Network (CAN), which is widely used in automotive and industrial applications. It supports both standard (11-bit ID) frames and extended (29-bit ID) frames. 【Specifications (Excerpt)】 ■ Designed based on ISO 11898-1:2015 ■ Supports CAN 2.0B and CAN FD frames ■ Supports data frames of up to 64 bytes ■ Supports flexible data rates ■ Supports emotas CANopen FD Stack *For more details, please download the PDF or feel free to contact us.

• ASIC

The "CAN Bus Controller [CAN-ALL]" is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. Developed as an ISO26262-10 Safety Element out of Context, it is available in two versions: Basic and Safety-Enhanced. Additionally, it can be improved with the necessary safety mechanisms as an option, and detailed safety documentation can be provided. 【Specifications (Excerpt)】 ■ Designed based on ISO 11898-1:2015 ■ Supports CAN 2.0B and CAN FD frames ■ Supports data frames of up to 64 bytes ■ Supports flexible data rates ■ Supports emotas CANopen FD Stack *For more details, please download the PDF or feel free to contact us.

• ASIC

The "AES-CTR Encryption IP Core" is an IP core for AES-CTR (Counter Mode) encryption that allows users to perform encryption/decryption of packets or data streams. It supports AES-CTR encryption levels of 128 or 256 bits and enables data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. Additionally, it is compatible with OpenSSL's AES-256-CTR encryption mode. 【Specifications】 ■ AES encryption key can be selected from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput ■ Compatible with OpenSSL's AES-256-CTR encryption mode *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce the 'AES-GCM Encryption IP Core' that we handle. This is an AES-GCM (Galois Counter Mode) encryption IP core that enables users to perform encryption/decryption and authentication of packets or data streams. It supports AES-GCM encryption levels of 128 or 256 bits and is capable of data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. 【Specifications】 ■ AES encryption key selectable from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce the 'AES-XTS Encryption IP Core' that we handle. This product is an AES-XTS encryption IP core that enables full disk encryption for storage devices. It supports AES-XTS encryption levels of 128-bit or 256-bit and allows encryption tailored to data transfer rates of SATA 6Gbps, SAS 12Gbps, and PCIe (NVMe) Gen4 x4 lanes. 【Specifications】 ■ FIPS-197 compliant AES-XTS algorithm ■ AES encryption key selectable from 128 or 256 bits ■ Configurable number of encoding/decoding pipelines ■ Independent management of encryption/decryption keys ■ Simultaneous support for encoding and decoding ■ Supports integer multiples of 16-byte data unit sizes *For more details, please download the PDF or feel free to contact us.

• ASIC

The "ECC with BCH Algorithm IP Core" is an IP core designed to add error detection/correction functionality using industry-standard BCH class error correction codes, preventing data loss or corruption over noisy and unreliable communication channels. If the BCH configuration is not covered, it can be customized to support a wide range of BCH codes. It can be used in a variety of applications, including data storage devices (SATA, SAS, FLASH), two-dimensional barcodes, satellite communication/telemetry, radio signal recording, wireless communication, high-speed modems such as ADSL and xDSL, and power line standards. 【Specifications】 ■ High bandwidth and low latency through parallel processing ■ Configurable encoding/decoding block structure ■ Configurable word length/block size ■ FIFO data interface of 32, 64, 128, or 256 ■ Parallelized BCH encoder/decoder *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce the 'NVMe-to-SATA Bridge' handled by Fujisoft Inc. This product is an IP core for creating an NVMe-to-SATA protocol bridge using NVMe Host IP core and SATA AHCI Host IP core. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. 【Specifications (Excerpt)】 ■ NVMe protocol interface complies with NVMe 1.4 standard ■ SATA interface complies with SATA 3.3 specification ■ Supports industry-standard AHCI (Advanced Host Controller Interface) v.1.3.1 ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks *For more details, please download the PDF or feel free to contact us.

• ASIC

The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce the "NVMe Host Accelerator IP Core" that we handle. This product is an NVMe host IP core from IntelliProp that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) with 8 lanes. It also features queuing and issuing capabilities for NVMe commands, allowing you to use it as a solution for high-speed data access to NVMe target devices. 【Specifications (excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Supports automatic initialization using PCIe hard blocks ■ Compatible with third-party PCIe Root Complex IP cores ■ Number of queues is adjustable (up to 64K) ■ Maximum data buffer size of 1GB *For more details, please download the PDF or feel free to contact us.

• ASIC

The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

• ASIC

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

• ASIC

The "IP Core for SATA RAID for FPGA/ASIC" provides RAID 0 (striping and concatenation) and splits data across multiple storage endpoints to achieve higher system storage performance. It is designed to operate with extremely low latency during data transfers between SATA storage devices and backend data interfaces. This can be used for RAID 0 storage solutions that require high speed and large capacity. 【Specifications (excerpt)】 - Supports RAID 0 (striping and concatenation) - Operates with an even number of drives - SATA transfer rates: 1.5Gbps, 3.0Gbps, and 6.0Gbps (supports automatic speed negotiation) *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

• ASIC

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

• ASIC

We would like to introduce our "SATA Host APP IP Core for FPGA and ASIC." This is an IP core for SATA hosts that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It consists of the PHY layer, LNK layer, TRN (Transport) layer, application layer, SerDes, and FIFO interface. 【Specifications】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Uses FIFO for the DATA interface ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

• ASIC

The "TI AM62Ax Based OSM-LF Module iW-RainboW-G55M" features a dual Arm Cortex-A72 processor @2GHz and four Arm Cortex-R5F cores, providing excellent computing power. It supports a variety of high-speed interfaces (such as PCIe and SGMII) and operates within a temperature range of -40°C to +85°C. Additionally, it is equipped with 2GB of LPDDR4 memory (expandable up to 8GB) and 16GB of eMMC flash. 【Features (partial)】 ■ AM62Ax with 64-Bit Quad Arm Cortex-A53 ■ Dual core ARM Cortex-R5F Subsystem ■ 2GB LPDDR4 Expandable up to 8GB and 16GB eMMC Flash ■ C7xV-256 Deep Learning Accelerator (2 TOPS) *For more details, please download the PDF or feel free to contact us.

• Embedded Board Computers
• Other embedded systems (software and hardware)

The "TI DRA821Ux Based OSM SoM iW-RainboW-G59M" features a dual Arm Cortex-A72 processor at 2GHz and four Arm Cortex-R5F cores, providing excellent computational power. Additionally, it is equipped with 2GB of LPDDR4 memory (expandable up to 8GB) and 16GB of eMMC flash. It also supports a variety of high-speed interfaces (PCIe, SGMII, USB 3.0, RGMII, CAN, I2C, SPI, etc.) and operates within a temperature range of -40°C to +85°C. 【Features】 ■ AM62Lx with 64-Bit Dual Arm Cortex-A53 ■ 1GB LPDDR4 expandable up to 2GB ■ 8GB eMMC Flash expandable ■ 2 x 1Gb RGMII ■ OSM v1.2 Size-SF LGA Solderable Module ■ Form Factor: 30mm x 30mm *For more details, please download the PDF or feel free to contact us.

• Embedded Board Computers
• Other embedded systems (software and hardware)

The "Zynq UltraScale+ MPSoC (ZU7/ZU5/ZU4) 3U-VPX Plug-in Module iW-RainboW-G30V" is equipped with AMD Xilinx's ZU7/5/4 Zynq UltraScale+ MPSoC. Additionally, it provides up to 504K logic cells and 230K LUTs, along with 64-bit 4GB PS DDR4 RAM with ECC (expandable up to 8GB) and 16-bit 1GB PL DDR4 RAM (expandable up to 2GB). It also offers 8GB eMMC flash (expandable up to 128GB) and various interfaces (Gigabit Ethernet, USB 3.0, USB 2.0, PCIe Gen3, etc.). 【Features (partial)】 ■ 16bit, 1GB PL DDR4 RAM (Upgradable) ■ 8GB eMMC Flash (Upgradable) *For more details, please download the PDF or feel free to contact us.

• Embedded Board Computers
• Other embedded systems (software and hardware)

The "Zynq Ultrascale+ MPSoC (ZU19/17/11EG) 3U VPX Plug-in Module iW-RainboW-G35V" provides up to 1,842K logic cells and 842.4K LUTs. Additionally, it features dual 64-bit, ECC-enabled 4GB FPGA-DDR4 memory (expandable up to 16GB) and a dual-core 1.2GHz ARM Cortex-A7 processor, along with 2GB DDR4 memory (ECC-enabled). It offers up to 32.75Gbps FPGA GTY transceivers with 31 channels and 8 optical transceivers (compliant with VITA66.4). [Features (partial)] ■ AMD Xilinx’s ZU19/17/11EG Zynq Ultrascale+ MPSoC ■ 64bit, 8GB PS DDR4 RAM with ECC (Upgradable) ■ Dual 64 bit, 8GB PL DDR4 RAM (Upgradable) *For more details, please download the PDF or feel free to contact us.

• Embedded Board Computers
• Other embedded systems (software and hardware)

The "KU19P Kintex UltraScale+ 3U VPX Plug-in Module iW-RainboW-G47V" is equipped with AMD Xilinx's KU19P, KU095, and KU115 Kintex UltraScale+ FPGAs, providing up to 1,842K logic cells and 842.4K LUTs. Additionally, it features dual 64-bit, ECC-enabled 4GB FPGA-DDR4 memory (expandable up to 16GB) and a dual-core 1.2GHz ARM Cortex-A7 processor, along with 2GB DDR4 memory (ECC-enabled) for the CPU. It offers up to 32.75Gbps FPGA GTY transceivers with 31 channels and 8 optical transceivers (VITA66.4 compliant). [Features (partial)] ■ Dual ARM Cortex-A7 core processor of 1.2GHz speed ■ 32bit 2GB DDR4 for CPU with ECC *For more details, please download the PDF or feel free to contact us.

• Embedded Board Computers
• Other embedded systems (software and hardware)