September 9 (Tuesday) Webinar "Fundamentals of Chiplet Implementation and Testing/Evaluation Techniques"
Chiplets are a technology that integrates multiple chips into a single package, necessitating new testing methods not only for traditional chip-level testing but also specifically for chiplets. This course will introduce the fundamental technologies of electronic circuit testing, followed by an overview of chiplets, the concepts of chiplet testing, testing methods for true KGD (Known Good Die) selection, challenges and latest trends in wafer probing, testing of interposers, system-level testing, SDC (Silent Data Corruption), boundary scan for chiplet interconnect testing and the IEEE 1838 standard, TSV connection failure repair methods and the UCIe standard, as well as new measurement methods to evaluate ultra-narrow pitch TSV connections such as hybrid bonding.
Target Audience for the Seminar:
Individuals interested in the implementation and testing of chiplets.
Knowledge Gained from the Seminar:
- Basic knowledge of electronic circuit testing
- Overview of chiplets
- Concepts and trends in chiplet testing
- Basic knowledge of boundary scan and chiplet testing standard IEEE 1838
- TSV connection failure avoidance technologies and UCIe standard
- New evaluation techniques for TSV connections using analog boundary scan

Date and time | Tuesday, Sep 09, 2025 01:30 PM ~ 04:30 PM This seminar will be a live-streaming seminar using "Zoom." |
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Entry fee | Charge |
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