FPGA Development Integrated Environment Active-HDL

Code coverage is the most commonly used effective method to verify the comprehensiveness of verification. However, coverage such as topological paths cannot be guaranteed. Functional coverage is a coverage method provided by SystemVerilog, which serves as a user-defined metric to measure the comprehensiveness of design specifications verified through simulation execution. It is measured using SystemVerilog assertions and Covergroup descriptions for the design features listed in the verification plan and is used for advanced verification of complex designs. In this webinar, we will introduce SystemVerilog's functional coverage and discuss techniques for its description.

The AXI4 Stream protocol is used as a standard interface for exchanging data between connected IPs within FPGA designs. When crossing clock domains, the AXI4 Stream interconnect is based on a switch that can transfer data to another asynchronous clock domain. The ALDEC_CDC rule plugin includes numerous rules for checking design quality, design constraints, and clock and reset trees. It is used for verifying the synchronous circuits of the design. However, static CDC verification methods alone may not guarantee the completeness of CDC verification tasks, making dynamic CDC verification essential. The main techniques for dynamic CDC verification include checks using CDC assertions and modeling random delay insertion during clock domain crossing. In this webinar, both static and dynamic verification methods for CDC verification of AXI4 Stream-based IP will be introduced, and the design and usage of CDC assertions automatically generated from ALINT-PRO, along with synchronizer models equipped with random delay insertion, will be explained.

Many hardware designers use RTL design methodologies for the development of various applications. However, verification of large-scale designs requires higher levels of abstraction, such as functional coverage, constrained random, and UVM. To achieve this, object-oriented programming (OOP) is essential, but hardware designers often have limited opportunities and time to engage with it. In this seminar, we will introduce SystemVerilog classes and object-oriented programming using simple examples.

With the evolution of FPGA technology, traditional programmable logic areas have been supplemented by CPUs, GPUs, and high-speed peripherals, making design verification increasingly challenging. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this final installment of the webinar series, we will introduce advanced verification solutions such as scoreboards, checkers, functional coverage, and assertions. We will also cover transaction-based debugging and unit linting features, as well as regression testing using Riviera-PRO.