High-speed HDLC/SPI communication firmware OP-FW10XR

basic information

By processing all communication data and timestamp measurements with FPGA, we achieve microsecond-level timestamps and reliable high-speed data capture. By expanding the count bit length of timestamps compared to the conventional analyzer's extended firmware, we can observe without overflow as long as the communication frame interval is within approximately 134 seconds at a 1μs resolution (previously, overflow occurred at 0.5 seconds with a 1μs resolution). Additionally, we can output a pulse to the external trigger terminal when a communication trigger is established, enabling collaboration with external measuring instruments such as oscilloscopes. For HDLC half-duplex communication like CC-Link, the HDLC communication frame is easily displayed by distributing it to TXD and RXD based on the address data of the first two bytes following the flag sequence. Both HDLC and SPI communication support not only data observation but also a simulation function that allows arbitrary data transmission. SPI can simulate four transfer modes with different data and clock phase in either master mode or slave mode.

Price range

P2

Delivery Time

P1

※Standard stock available.

Applications/Examples of results

We supply numerous products to research institutes that develop products for most major electronics manufacturers, quality control departments that inspect communication performance during product shipment for major machinery manufacturers, technical service departments for communication equipment and computer manufacturers, maintenance departments for communication systems within buildings and factories, and maintenance departments for major telecommunications operators both domestically and internationally. Additionally, due to its ease of use, it is utilized not only by hardware engineers but also by software engineers. Its compact and lightweight design is particularly appreciated by those in field maintenance and service departments.