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DapTechnology FireCore (IP Core)

DapTechnology FireCore (IP Core)

FireCore is an IP core that integrates PHY and link layer controller (LLC) cores into a single IP product.

FireCore integrates the PHY and link layer requirements necessary for common 1394 devices into a single IP core. Based on the FireGate PHY IP core and FireLink LLC IP core, FireCore is designed to support data rates from S100 to S3200 and various host interfaces such as generic, OHCI, and OHCI (with AS5643 option). DapTechnology's new FireCore package offers unprecedented technical capabilities, features, flexibility, and options for customization and future expansion. Together with FireStack (DapTechnology's 1394 software stack), FireCore is designed to fully leverage the capabilities of the AS5643 extension. It aims to completely abstract the 1394 protocol layer and the AS5643 protocol layer, allowing implementers to focus entirely on system-level functionalities such as fault tolerance, fault isolation, and redundancy.

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DapTechnology's FireGate PHY Layer Core

DapTechnology's FireGate PHY Layer Core

FireGate is an IP core that complies with IEEE-1394b and supports all AS5643 requirements.

Advantages of implementing a complete 1394 I/O interface using FPGA Standalone solution: By combining PHY IP with link layer IP, it is possible to create smaller products. Additional components can be added to create a system-on-chip (SoC) solution. Flexible number of ports: Commercially available PHY chips have a fixed number of ports, which is often excessive for small peripherals. On the other hand, host adapters are likely to benefit from three or more ports, and hubs can have even more ports. In the case of PHY based on FPGA technology, users can customize the number of ports as needed. Optional debugging and testing features: Optionally, debugging and testing features such as BERT (Bit Error Rate Testing) can be included. Field upgradable: The FPGA used is field-upgradable, allowing new features and bug fixes to be added even when the device is already in the field. Cost-effective ASICs: Once the design is complete, the IP solution provides a very cost-effective way to spin custom ASICs.

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[Information] Shirutoku Report No. 95 # Effective Components for Noise Countermeasures

[Information] Shirutoku Report No. 95 # Effective Components for Noise Countermeasures

I will talk about the noise countermeasures in the evaluation of power converters!

★★Shirutoku Report: Useful Information You Can Benefit From★★ The current task is the evaluation of "power conditioners" (hereinafter referred to as power conditioners). When we talk about "evaluation of power conditioners," there are various types of evaluations, but this time I would like to discuss the noise countermeasures implemented in our recent work. Please take a moment to read it. [Contents] ■ Causes of Noise Generation ■ Noise Countermeasure Component "Core (Core Material of the Coil)" *For more details, please refer to the PDF document or feel free to contact us.

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IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

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DapTechnology FireLink LLC IP Core

DapTechnology FireLink LLC IP Core

FireLink is a link layer controller IP core compliant with IEEE-1394b.

FireLink, a synthesizable IEEE-1394-2008 beta link layer controller (LLC) core, is based on the link layer controller that has been used in DapTechnology's FireSpy analyzer products for several years. FireLink is a mature core implemented on FPGAs from Xilinx, Altera, and Microsemi. FireLink is available in three configurations: Basic, Extended, and GPLink. ■Japanese technical documentation for AS5643 is available. If you would like to see it, please contact sales@nacelle.co.jp■

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