Free Webinar: Designing Finite State Machines for Safety-Critical Systems
In safety-critical design control logic, finite state machines (FSM) are an important component. When the FPGA within the system is operating, external factors such as single event upsets or radiation can cause the bit values stored in the FSM registers to change to incorrect values in a nondeterministic manner, potentially leading to system malfunctions or failures. Furthermore, with the miniaturization of transistors, this issue has become more common. In this webinar, we will introduce various methods for developing robust and safe FSMs, from best practices in FSM design to reliable FSM design techniques.

| Date and time | Wednesday, May 28, 2025 03:00 PM ~ 04:00 PM |
|---|---|
| Entry fee | Free |
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