RTL Code Analysis and Verification Solution ALINT-PRO

In high-speed FPGA design, not only high clock frequencies are required, but also carefully optimized RTL design. Advanced linting becomes a static RTL code analysis process that detects hidden issues in the code against hundreds of design rules. In addition to improving code quality, advanced linting directly contributes to performance optimization, which is a critical factor in achieving frequency, power consumption, and area targets for high-speed FPGA designs. ALINT-PRO helps designers identify and fix potential bottlenecks early in the design cycle, contributing to the reduction of time-consuming implementation and timing closure with FPGA vendor tools. This webinar will introduce how to apply and the effects of advanced linting using ALINT-PRO.

In conventional ASIC/FPGA designs, simple resets such as power-on reset and warm reset were used to reset the design to a known state. However, due to current trends in low power consumption, error recovery in critical safety designs, and debugging applications, multiple resets are now incorporated and controlled by software (or hardware). In this webinar, we will introduce the metastability issues caused by resets and the RDC issues.

The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standard, how it will be implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. In this webinar, we will demonstrate the use of ALINT-PRO to enforce coding standards and highlight the benefits of streamlining the overall design review to meet the objectives of DO-254.

In today's large-scale ASIC/FPGA design, clock domain crossing verification is one of the important tasks. Many designs include a large number of third-party IPs, and their source code may be encrypted or non-encrypted. It is crucial to perform clock domain crossing verification for designs that include such encrypted IPs, which necessitates the preparation of an abstraction model for encrypted IP cores. Furthermore, as the design scale increases, it becomes impractical to analyze the entire system at once. It is more reasonable to verify individual leap design modules using a partitioned analysis approach and to abstract the verified modules when performing system-level analysis. This webinar will introduce the development method of abstraction models for encrypted IPs and how to analyze large-scale designs using the abstracted leap design module models.