RTL Code Analysis and Verification Solution ALINT-PRO

Recent hardware design has seen an increase in scale and complexity, which may lead to prolonged design verification processes. In this context, there is growing attention on cleaning up design code before design verification. Cleanup can be performed relatively quickly and significantly reduces the time and effort required for design verification. Additionally, as SystemVerilog (design) becomes more prevalent in hardware design, the importance of checking design code using these tools is also increasing. ALINT-PRO can statically verify most common SystemVerilog (design) elements, allowing for the early detection of critical design issues in the design cycle. In this webinar, we will introduce the issues related to SystemVerilog and the rules for checking them.

The AXI4 Stream protocol is used as a standard interface for exchanging data between connected IPs within FPGA designs. When crossing clock domains, the AXI4 Stream interconnect is based on a switch that can transfer data to another asynchronous clock domain. The ALDEC_CDC rule plugin includes numerous rules for checking design quality, design constraints, and clock and reset trees. It is used for verifying the synchronous circuits of the design. However, static CDC verification methods alone may not guarantee the completeness of CDC verification tasks, making dynamic CDC verification essential. The main techniques for dynamic CDC verification include checks using CDC assertions and modeling random delay insertion during clock domain crossing. In this webinar, both static and dynamic verification methods for CDC verification of AXI4 Stream-based IP will be introduced, and the design and usage of CDC assertions automatically generated from ALINT-PRO, along with synchronizer models equipped with random delay insertion, will be explained.

Henderson, NV – January 14, 2026 – Aldec, Inc., a pioneer in mixed HDL language simulation and verification solutions for FPGA and ASIC design, today announced the release of ALINT-PRO 2025.12, which provides new design rules and guidance for mixed-language projects. This update will help engineering teams improve accuracy, maintainability, and IP interoperability when combining VHDL and Verilog/SystemVerilog within a single project. As mixed-language development becomes common for IP reuse, third-party integration, and long-term product maintenance, design teams face challenges caused by ambiguous mappings, inconsistent parameter passing, and misuse of configurations. ALINT-PRO 2025.12 reduces these risks by applying a concentrated set of best practice rules aimed at preventing integration issues before simulation, logic synthesis, and downstream verification. Please refer to the attached document for more details.

Most FPGA designs include configurable IP blocks provided by FPGA vendors. These IP blocks may contain synthesizable RTL code. In CDC verification, pseudo violations can occur due to this IP, leading to increased analysis time. In this webinar, we will introduce how to describe constraints for IP using block-level constraints in ALINT-PRO.