RTL Code Analysis and Verification Solution ALINT-PRO

The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standard, how it will be implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. In this webinar, we will demonstrate the use of ALINT-PRO to enforce coding standards and highlight the benefits of streamlining the overall design review to meet the objectives of DO-254.

In today's large-scale ASIC/FPGA design, clock domain crossing verification is one of the important tasks. Many designs include a large number of third-party IPs, and their source code may be encrypted or non-encrypted. It is crucial to perform clock domain crossing verification for designs that include such encrypted IPs, which necessitates the preparation of an abstraction model for encrypted IP cores. Furthermore, as the design scale increases, it becomes impractical to analyze the entire system at once. It is more reasonable to verify individual leap design modules using a partitioned analysis approach and to abstract the verified modules when performing system-level analysis. This webinar will introduce the development method of abstraction models for encrypted IPs and how to analyze large-scale designs using the abstracted leap design module models.

ALINT-PRO provides a powerful means for static analysis and verification of clock domain crossing (CDC). It detects and verifies clock trees and clock domains, applying topological pattern matching techniques to validate the design structure over clock domain crossings. However, to ensure that there are no CDC-related issues, it is necessary to add dynamic CDC verification using a simulator in addition to static CDC verification. ALINT-PRO can enhance functional verification by generating check code for CDC points with its assertion generation engine. In this webinar, we will introduce a complete clock domain crossing verification methodology, from static verification using ALINT-PRO to dynamic verification using Riviera-PRO.

In safety-critical design control logic, finite state machines (FSM) are an important component. When the FPGA within the system is operating, external factors such as single event upsets or radiation can cause the bit values stored in the FSM registers to change to incorrect values in a nondeterministic manner, potentially leading to system malfunctions or failures. Furthermore, with the miniaturization of transistors, this issue has become more common. In this webinar, we will introduce various methods for developing robust and safe FSMs, from best practices in FSM design to reliable FSM design techniques.