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  6. RTL Code Analysis and Verification Solution ALINT-PRO

RTL Code Analysis and Verification Solution ALINT-PRO

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last updated:Dec 23, 2020

アルデック・ジャパン
アルデック・ジャパン
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Static design analysis tool that works on Windows/Linux.

"ALINT-PRO" is a verification solution that analyzes RTL code written in VHDL, Verilog, and SystemVerilog, focusing on coding styles and naming conventions, mismatches between RTL and synthesis results, smooth and optimal synthesis, correct FSM descriptions, issues in the later stages of design, problems with clock and reset trees, CDC, RDC, DFT, and coding for portability and reuse. This solution performs static analysis based on RTL and SDC (Synopsys Design Constraints) source files, identifying critical design issues early in the design phase and significantly contributing to the reduction of design time. By running ALINT-PRO before RTL simulation and logic synthesis, you can prevent design issues from propagating to downstream processes in the design flow, thereby reducing the number of revisions needed before design completion. *For more details, please refer to the PDF materials or feel free to contact us.*

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ALINT-PRO.jpg

RTL Code Analysis and Verification Solution ALINT-PRO

ALINT-PRO.jpg
ALINT-PRO.jpg
  • Related Link - https://www.aldec.com/jp/products/functional_verif…

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basic information

**Features** - Verification solution for analyzing RTL code - Early detection of bugs in the design flow - Comprehensive rule library - Support for design constraints - Clarification of problem areas through static verification checks **Main Functions** - Analysis of clock, reset, and network - Prevention of mismatches between RTL simulation and post-synthesis simulation - Code portability and reusability - Verification of FSM description accuracy - Graphical analysis of detected FSMs and identified FSM issues - Schematic viewer - Support for industry-standard design style guides (STARC/RMM) - Extensive CDC and RDC checks via ALDEC_CDC rule plugin - Static verification rule set focused on RISC-V - Advanced CDC and RDC debugging environment - SDC support - Design constraint extensions for IP descriptions *For more details, please refer to the PDF document or feel free to contact us.*

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Delivery Time

P3

Applications/Examples of results

Improvement of RTL design quality, enhancement of reusability, prevention of mismatches between RTL simulation and post-synthesis simulation, and improvement of the safety of asynchronous transfer.

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RTL Code Analysis and Verification Solution ALINT-PRO

RTL Code Analysis and Verification Solution ALINT-PRO

PRODUCT
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[Information] Clock Domain Crossing in the World of FPGA

[Information] Clock Domain Crossing in the World of FPGA

TECHNICAL
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[Information] Reset and Reset Domain Crossing in ASIC and FPGA Design

[Information] Reset and Reset Domain Crossing in ASIC and FPGA Design

TECHNICAL
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[Information] Achieving Equivalence Between RTL and Netlist: Lint is Essential!

[Information] Achieving Equivalence Between RTL and Netlist: Lint is Essential!

TECHNICAL
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[Information] Optimal Design Methods for Large Capacity FPGA Devices

[Information] Optimal Design Methods for Large Capacity FPGA Devices

TECHNICAL
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[Data] RISC-V design linting using ALINT-PRO

[Data] RISC-V design linting using ALINT-PRO

TECHNICAL
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News about this product(20)

Free Webinar: ALINT-PRO Block-Level Constraints for CDC Verification

  • Seminar・Event

Most FPGA designs include configurable IP blocks provided by FPGA vendors. These IP blocks may contain synthesizable RTL code. In CDC verification, pseudo violations can occur due to this IP, leading to increased analysis time. In this webinar, we will introduce how to describe constraints for IP using block-level constraints in ALINT-PRO.

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Free Webinar: Optimizing Design Performance through Advanced Static Linting

  • Seminar・Event

In high-speed FPGA design, not only high clock frequencies are required, but also carefully optimized RTL design. Advanced linting becomes a static RTL code analysis process that detects hidden issues in the code against hundreds of design rules. In addition to improving code quality, advanced linting directly contributes to performance optimization, which is a critical factor in achieving frequency, power consumption, and area targets for high-speed FPGA designs. ALINT-PRO helps designers identify and fix potential bottlenecks early in the design cycle, contributing to the reduction of time-consuming implementation and timing closure with FPGA vendor tools. This webinar will introduce how to apply and the effects of advanced linting using ALINT-PRO.

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Free Webinar: Analysis of Reset and RDC Issues by ALINT-PRO

  • Seminar・Event

In conventional ASIC/FPGA designs, simple resets such as power-on reset and warm reset were used to reset the design to a known state. However, due to current trends in low power consumption, error recovery in critical safety designs, and debugging applications, multiple resets are now incorporated and controlled by software (or hardware). In this webinar, we will introduce the metastability issues caused by resets and the RDC issues.

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Free Webinar: Thorough Examination of HDL Coding Standards in DO-254 Projects

  • Seminar・Event

The RTCA/DO-254 guidance recommends that applicants define and implement HDL coding standards. This work begins with a planning process that includes the definition of the standard, how it will be implemented, and, if the process is automated, the evaluation methods for tools or results. A key issue is that the guidance does not have clearly defined formal standards, leading to questions about how to conduct a detailed review of HDL code. In this webinar, we will demonstrate the use of ALINT-PRO to enforce coding standards and highlight the benefits of streamlining the overall design review to meet the objectives of DO-254.

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アルデック・ジャパン

アルデック・ジャパン

IT/Telecommunications

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Aldec Japan, Inc. is a leading EDA tool vendor in the industry, releasing innovative design creation, simulation, verification solutions, and a variety of development boards, which are adopted for the development of large-scale FPGA/ASIC/SoC and embedded system designs. The fields we are involved in span various areas, including telecommunications, automotive, educational and research institutions, and the aerospace industry. Please feel free to contact us if you have any inquiries.

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