Free Webinar: Hierarchical Approach Analysis Using ALINT-PRO

In today's large-scale ASIC/FPGA design, clock domain crossing verification is one of the important tasks. Many designs include a large number of third-party IPs, and their source code may be encrypted or non-encrypted. It is crucial to perform clock domain crossing verification for designs that include such encrypted IPs, which necessitates the preparation of an abstraction model for encrypted IP cores. Furthermore, as the design scale increases, it becomes impractical to analyze the entire system at once. It is more reasonable to verify individual leap design modules using a partitioned analysis approach and to abstract the verified modules when performing system-level analysis. This webinar will introduce the development method of abstraction models for encrypted IPs and how to analyze large-scale designs using the abstracted leap design module models.

Date and time | Wednesday, Jul 30, 2025 03:00 PM ~ 04:00 PM |
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Entry fee | Free |
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