Free Webinar: Analysis of Reset and RDC Issues by ALINT-PRO

In conventional ASIC/FPGA designs, simple resets such as power-on reset and warm reset were used to reset the design to a known state. However, due to current trends in low power consumption, error recovery in critical safety designs, and debugging applications, multiple resets are now incorporated and controlled by software (or hardware). In this webinar, we will introduce the metastability issues caused by resets and the RDC issues.

Date and time | Wednesday, Sep 17, 2025 03:00 PM ~ 04:00 PM |
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Entry fee | Free |
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