『CDCI6214』

PCIe Gen4 compatible, ultra-low power clock generator 'CDCI6214'

The CDCI6214 is a configurable high-performance PLL with four programmable outputs. It selects from two independent reference inputs to the phase-locked loop and generates up to four differential frequencies on configurable differential output channels while also producing a copy of the reference clock on LVCMOS output channels. Each of the four output channels features a configurable integer/fractional output divider and a dedicated integer divider. Together with the output multiplexer, it enables up to five differential frequencies. The clock distribution divider is reset in a deterministic manner for clean clock gating and glitch-free updates. Flexible power-down options allow for optimization, minimizing power consumption during both active operation and standby. The power consumption of four 156.25MHz LVDS outputs is 150mW (typical) at 1.8V. An RMS jitter of 386fs (typical) for the 100MHz HCSL output enhances the system margin for PCIe applications. *For more details, please contact us.*

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