High-speed RTL simulator "Riviera-PRO"

With the evolution of FPGA technology, traditional programmable logic areas have been supplemented by CPUs, GPUs, and high-speed peripherals, making design verification increasingly challenging. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this final installment of the webinar series, we will introduce advanced verification solutions such as scoreboards, checkers, functional coverage, and assertions. We will also cover transaction-based debugging and unit linting features, as well as regression testing using Riviera-PRO.

With the evolution of FPGA technology, traditional programmable logic domains have been supplemented by CPUs, GPUs, and high-speed peripherals, making design verification increasingly challenging. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this webinar, we will outline advanced simulation-based verification processes, FPGA-centric verification processes, and how to create verification plans, including what to verify and how to do so.

Although I have heard that verification efficiency at the RTL stage improves with verification methodologies using SystemVerilog such as UVM, many designers may not fully understand what can be done with SystemVerilog and how to use it. In this seminar, we will introduce the basic functions and usefulness of SystemVerilog verification using a sample design. 1. Design Overview 2. UART Test Environment 3. Assertions (SVA & PSL) 4. Functional Coverage 5. Random Test Bench 6. DPI-C

Requirements-based verification is a common verification process for FPGA designs used in safety-critical systems. The effectiveness of requirements-based verification depends on the quality and accuracy of the requirements. Verification methods such as constraint-based random verification using assertion-based verification help identify ambiguous or incomplete requirements early in the design and verification process. Additionally, assertions can enhance the observability of the design, significantly reducing debugging time. This increases the time available for exploring new bugs, leading to improved verification quality. In this webinar, we will introduce how to optimize and verify requirements using SystemVerilog assertions.