High-speed RTL simulator "Riviera-PRO"

Although I have heard that verification efficiency at the RTL stage improves with verification methodologies using SystemVerilog such as UVM, many designers may not fully understand what can be done with SystemVerilog and how to use it. In this seminar, we will introduce the basic functions and usefulness of SystemVerilog verification using a sample design. 1. Design Overview 2. UART Test Environment 3. Assertions (SVA & PSL) 4. Functional Coverage 5. Random Test Bench 6. DPI-C

Requirements-based verification is a common verification process for FPGA designs used in safety-critical systems. The effectiveness of requirements-based verification depends on the quality and accuracy of the requirements. Verification methods such as constraint-based random verification using assertion-based verification help identify ambiguous or incomplete requirements early in the design and verification process. Additionally, assertions can enhance the observability of the design, significantly reducing debugging time. This increases the time available for exploring new bugs, leading to improved verification quality. In this webinar, we will introduce how to optimize and verify requirements using SystemVerilog assertions.

Constraint random and functional coverage using SystemVerilog are widely used by many designers, but the simulators that support these features tend to be expensive products. Cocotb, which uses Python as a verification language, makes it easy to utilize these features and provides designers who have not been able to try them with an opportunity to challenge new verification methods. In this webinar, we will introduce two approaches for using constraint random and functional coverage with cocotb.

Typically, hardware designers are very busy and have little time to try out new methodologies. Unfortunately, the official documentation for UVM (Universal Verification Methodology) is written by verification engineers for verification engineers, focusing on high-level functionality while ignoring lower-level details such as connecting the UVM testbench to the design. In this webinar, we will explain the main UVM components such as Sequencer and Driver using a simple design and virtual interfaces.