We will introduce examples of implementing heat-resistant fragile chip mounting, low thermal stress mounting, and large chip mounting.
We would like to introduce a case study of our response to chip manufacturers. Even though they developed high-performance and high-functionality chips for sensors, high-speed communication, processors, etc., they faced challenges such as not having a subcontractor for implementation to realize those functions, being unable to implement thermally fragile chips, and being unable to implement large-area chips. As a result, we carried out implementations for thermally fragile chips, low thermal stress implementations, and large chip implementations. [Case Overview (Excerpt)] ■ Implementation of thermally fragile chips - Achieved implementation of a 140°C heat-resistant magnetic sensor array ■ Low thermal stress implementation - Achieved implementation of a 40mm ultrasonic MEMS sensor chip *For more details, please refer to the PDF document or feel free to contact us.
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【Other Case Overview】 ■Large Chip Implementation - Capable of integrating a super chip with a size of 20mm square and memory *For more details, please refer to the PDF document or feel free to contact us.
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For more details, please refer to the PDF document or feel free to contact us.
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Connectec Japan Co., Ltd. is a process development-oriented semiconductor backend contract OSRDA that creates new packages through its core technologies, bump-on-material and damage-free bonding, known as MONSTER PAC. If you are facing challenges with semiconductor chip assembly or MEMS chip manufacturing and assembly, please consult us first. Our experienced development team will respond to any of your requests.