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In the early stages of development, a necessary "few to several dozen" prototypes. It is difficult for large companies to respond to this need, which is where our value lies. In large-scale companies like major foundries and OSATs that require significant investment recovery, mismatches in supply and demand for small-scale development projects tend to occur. "CADN" has established a decentralized production division model with small investments by organically connecting domestic legacy lines and research institutions. While hedging against regional risks such as earthquakes and floods, we have set up a system that can flexibly respond to a wide variety of structural and construction method requests. *For more details on the new business model "CADN," which consolidates Japan's manufacturing capabilities, please download here.
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We have developed a three-layer coplanar RDL substrate using low-loss insulating materials and simultaneously achieved high-precision bonding of millimeter-wave chips. We overcame technical challenges such as wrinkles and warping due to thermal expansion, as well as deposits during via processing, through thorough process improvements. By utilizing landless vias and three-layer impedance matching RDL, we ensured transmission characteristics over a wide bandwidth of 70 GHz. This is a top-tier example of realizing customer desires by managing 24 complex processes through the amoeba-like collaboration of 15 partner companies. *For detailed information on the millimeter-wave compatible implementation process and verification results, please refer to the downloadable materials.*
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We directly bonded memory chips and SOCs (COC) and responded to the advanced requirements of flip chip mounting onto package substrates. By coordinating the networks of four companies and ten processes, we successfully achieved bonding between heterogeneous chips of varying heights. Utilizing 40µm pitch copper pillar bonding and 90µm copper balls as spacers, we realized the shortest connections between chips and substrates. This structure, which maximizes signal transmission efficiency, provides a significant advantage in high-speed processing devices. *Details of the network that successfully integrates heterogeneous chips are illustrated in the accompanying materials.*
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The realization of high-sensitivity sensors requires extremely precise wafer processing technology to expand the light-receiving area. We conducted a special processing to form 1 million square holes with a 100µm pitch on a Φ200mm photodiode wafer. By maintaining square holes of 90µm and a thin wall structure of 10µm, we achieved an overwhelming large aperture ratio and successfully enhanced sensitivity. This is a fine processing solution unique to Connectec Japan, utilizing deep dry etching (DRIE) on silicon wafers. *The accuracy of wafer processing and detailed specifications are available in the downloadable materials.
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How to integrate heat-sensitive image sensors with high-speed processing LSI. We solved this challenge with our unique 3D stacking technology. By 3D stacking heat-sensitive X-ray image sensors and TSV-forming LSI at low temperatures, we achieved direct bonding of the sensor pixel signal terminals. By arranging 144 sensors, each measuring 10mm on a side, with a minimal gap of 50µm, we enable large-area and high-sensitivity sensing. This is a case that condenses our know-how in utilizing silicon interposers to maximize high-speed measurement processing. *For specific processes of advanced 3D stacking technology, please refer to the materials.
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We have achieved high-precision mounting on thermally fragile chips and film substrates, which was impossible with conventional solder mounting. Standard solder joints require high temperatures of 260°C, but MONSTER PAC enables low-temperature bonding at 80°C to 170°C using conductive paste. This suppresses thermal expansion of materials and allows for narrow pitches of less than 40μm and high-precision mounting of less than 3μm. It is a suitable method for mounting advanced devices sensitive to heat, such as magnetic sensors and MEMS. *You can download the technical details and specifications of MONSTER PAC from here.*
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We provide total support for special projects that are impossible on existing mass production lines, from the conceptual stage to mass production. OSRDA (Outsourced Semiconductor R&D Assembly) is a business model that distinguishes itself from mere assembly specialists (OSAT). We can handle any process related to implementation, from substrate design, process development, and prototyping to reliability testing, at any stage and from any point. We offer flexible solutions tailored to our customers' preferences, such as multi-variety variable production and the development of special applications. *Please take a look at the materials that explain the specific service flow of OSRDA.
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With the advancement of IoT, new challenges of "heat" and "precision" are being presented in semiconductor packaging. The number of IoT devices, which was about 25 billion in 2020, is expected to reach approximately 64 billion by 2030. Many of these devices are composed of chips and substrates that are sensitive to heat, making it difficult to address them with conventional high-temperature packaging. To realize the virtual world with physical hardware, innovative technologies that operate at low temperatures and low thermal stress are essential. *Data summarizing the market forecasts and packaging challenges for IoT can be obtained here.*
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We would like to introduce our philosophy of connecting companies, technology, and people to pave the way for the future of IoT implementation. Based in the semiconductor "back-end" hub that spans from the Joetsu region of Niigata Prefecture to Nagano Prefecture, we aim to create the world's first and best technologies. With our low-temperature packaging technology "MONSTER PAC" and fine wiring technology "FSNIP" as our weapons, we respond to various packaging needs. Together with like-minded colleagues, our mission is to contribute to society through job creation. *For more details on Connectec Japan's corporate philosophy and business overview, you can download it here.
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We would like to introduce a case study of our response to equipment manufacturers. When developing new process equipment, they faced challenges such as a lack of knowledge and development resources regarding the process, and the desire to sell the process and equipment as a package, but having processes that they do not own in-house. As a result, we conducted equipment development and low-temperature 80°C chip bonding for narrow-pitch PET substrates. [Case Overview] ■ Equipment Development - Equipment development tailored to specifications and budget requests. ■ Low-Temperature 80°C Chip Bonding for Narrow-Pitch PET Substrates - 27.5μm pitch wiring and bump formation (by Komori Corporation) - Low-temperature 80°C flip chip mounting *For more details, please refer to the PDF document or feel free to contact us.
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We would like to introduce a case study of our response to material manufacturers. We developed high-performance materials such as flexible, stretchable, and millimeter-wave materials. When being evaluated, they faced challenges such as forming wiring on films, low-temperature mounting on thermally fragile materials, and the desire to evaluate not just the materials alone but also with chips mounted. To address these issues, we conducted free-form wiring using a jet dispenser, developed optical transceiver methods, and evaluated millimeter-wave substrate materials compatible with 5G. [Case Overview] - Free-form wiring using a jet dispenser - Development of optical transceiver methods - Realization of compact AOC through FPC with integrated optical waveguides - Evaluation of 5G-compatible millimeter-wave substrate materials *For more details, please refer to the PDF document or feel free to contact us.
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We would like to introduce a case study of our response to chip manufacturers. Even though they developed high-performance and high-functionality chips for sensors, high-speed communication, processors, etc., they faced challenges such as not having a subcontractor for implementation to realize those functions, being unable to implement thermally fragile chips, and being unable to implement large-area chips. As a result, we carried out implementations for thermally fragile chips, low thermal stress implementations, and large chip implementations. [Case Overview (Excerpt)] ■ Implementation of thermally fragile chips - Achieved implementation of a 140°C heat-resistant magnetic sensor array ■ Low thermal stress implementation - Achieved implementation of a 40mm ultrasonic MEMS sensor chip *For more details, please refer to the PDF document or feel free to contact us.
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We would like to introduce a case study of our response to system and set manufacturers. Even if you have a concept for an IoT system or set, you may be facing challenges such as not knowing the implementation methods or materials to use, OSAT not being able to accommodate structures other than assembly line setups or small-scale production, and lacking a partner for process development that involves equipment development. As a result, we conducted narrow-pitch MEMS mounting on flexible substrates, flexible substrate mounting, and stress measurement for solder flip chips. [Case Summary (Excerpt)] ■ Narrow-pitch MEMS mounting on flexible substrates - Created flexible substrate design and implemented NCP/ACP mounting - Achieved miniaturization ■ Low-temperature 80℃ flexible substrate mounting *For more details, please refer to the PDF document or feel free to contact us.
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We would like to introduce our technology, 'FSNIP (Free Substrate material Narrow pitch Imprinted Process).' By transferring conductive paste onto a substrate using the imprinting method, we can simultaneously form wiring and bumps with a pitch of 40μm or less, with a minimum pitch of 10μm. Due to the transfer wiring method, it can be manufactured with low-cost equipment and in small area factories, and because wiring and bumps are formed simultaneously, it achieves an excellent method that does not result in alignment shifts. 【Features】 ■ Transfer of conductive paste onto the substrate using the imprinting method ■ Simultaneous formation of wiring and bumps with a pitch of 40μm or less, with a minimum pitch of 10μm ■ Can be manufactured with low-cost equipment and in small area factories ■ No alignment shifts occur *For more details, please refer to the PDF document or feel free to contact us.
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We would like to introduce our technology, "MONSTER PAC(R)." In the IoT sector, chips and film substrates, even if high-performance, have sometimes been unable to withstand solder mounting. Our technology achieves a mounting temperature of 80°C to 170°C through low-temperature bonding using conductive paste. This not only resolves the issue of bonding temperature but also frees materials from thermal expansion and contraction, enabling narrow pitches of 40μm or less and high-precision mounting of 3μm or less. 【Features】 ■ Low-temperature bonding using conductive paste ■ Achieves mounting temperatures of 80°C to 170°C ■ Frees materials from thermal expansion and contraction ■ Enables high-precision mounting *For more details, please refer to the PDF document or feel free to contact us.
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The "Desktop Flip Chip Bonder" enables the construction of a compact semiconductor assembly line without the need for a clean room by combining local clean technology. Since it does not use special chemicals and produces no noise, factories can be established anywhere. With a building the size of a convenience store, it is possible to freely construct a multi-variety, variable production line, allowing for a rapid response to market needs and the establishment of necessary production systems. 【Features】 ○ No clean room required ○ Factory miniaturization is achievable ○ Capable of multi-variety, variable production ○ Realizes Industry 4.0 For more details, please contact us or download the catalog.
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